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MPF7100BVMA2ES Datasheet(PDF) 58 Page - NXP Semiconductors |
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MPF7100BVMA2ES Datasheet(HTML) 58 Page - NXP Semiconductors |
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58 / 125 page ![]() NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 58 / 125 Symbol Parameter Min Typ Max Unit ISNVSx VSNVSx load current range 0 — 10 mA VSNVSx_ACC VSNVSx output voltage accuracy in LDO mode −5.0 — 5.0 % VSNVS1_RDSON VSNVS1 LDO on resistance VSNVS1VOLT[1:0] = 10 or 11 — — 20 Ω VSNVSx_IQ VSNVSx quiescent current in LDO mode — 5.0 — µA VSNVS1_HDR VSNVS1 LDO headroom voltage Minimum voltage above setting VSNVS1VOLT[1:0] = 10 or 11 to guarantee regulation with 5 % tolerance 200 — — mV VSNVS1_HDR VSNVS1 LDO headroom voltage Minimum voltage above setting VSNVS1VOLT[1:0] = 01 to guarantee regulation with 5 % tolerance 500 — — mV VSNVSx_OS VSNVSx startup overshoot — — 200 mV VSNVSx_TRANS VSNVSx load transient −100 — 100 mV VSNVSx_ILIM VSNVSx current limit 20 — 70 mA VSNVSx_TON VSNVSx turn on time Block enabled to VSNVSx at 90 % of final value — — 1.35 ms 15.3 Type 1 buck regulators (SW1 to SW4) The PF7100 features four low-voltage regulators with input supply range from 2.5 V to 5.5 V and output voltage range from 0.4 V to 1.8 V in 6.25 mV steps. Each voltage regulator is capable to supply 2.5 A and features a programmable soft-start and DVS ramp for system power optimization. aaa-028064 I2C INTERFACE 2 to 3 MHz clock duty cycle generator slope compensation DAC R2 R1 EA SWxFB TYPE II INTERNAL COMPENSATION VSWx SWxLX SWxIN SWx VIN CINSWx COSWx LSWx SWxPHASE SWxILIM SWxMODE CONTROLLER DRIVER ISENSE Z2 + + Figure 25. Buck regulator block diagram |
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