MPF7100BVMA2ES datasheet(59/125 Pages) NXP

59 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 9 March 2021

59 / 125

The OTP_SWxDVS_RAMP bit sets the default step/time ratio for the power up ramp

during the power up/down sequence as well as the DVS slope during the system-on.

The power down ramp and DVS rate during the system on of SW1 to SW4 can be

modified during the system-on states by changing the SWxDVS_RAMP bit on the I2C

The DVS ramp rate is based on the internal clock configuration as shown in the following

table:

Table 42. SW1 to SW4 ramp rates

All ramp rates are typical values. Clock frequency tolerance = ± 5 %.

CLK_

FREQ[3:0]

Clock

frequency

(MHz)

Regulators

frequency

(MHz)

SWxDVS_RAMP =

DVS_Up (mV/µs) /

DVS_Down (mV/

µs)

SWxDVS_RAMP =

DVS_Up (mV/µs) /

DVS_Down (mV/

µs)

SWxDVS_RAMP =

DVS_Up (mV/µs) /

DVS_Down (mV/

µs)

SWxDVS_RAMP =

DVS_Up (mV/µs) /

DVS_Down (mV/

µs)

0000

2.500

7.81 / 5.21

15.63 / 10.42

3.91 / 2.60

1.95 / 1.30

0001

2.625

8.20 / 5.47

16.41 / 10.94

4.10 / 2.73

2.05 / 1.37

0010

2.750

8.59 / 5.73

17.19 / 11.46

4.30 / 2.86

2.15 / 1.43

0011

2.875

8.98 / 5.99

17.97 / 11.98

4.49 / 2.99

2.25 / 1.50

0100

3.000

9.38 / 6.25

18.75 / 12.50

4.69 / 3.13

2.34 / 1.56

1001

2.000

6.25 / 4.17

12.50 / 8.33

3.13 / 2.08

1.56 / 1.04

1010

2.125

6.64 / 4.43

13.28 / 8.85

3.32 / 2.21

1.66 / 1.11

1011

2.250

7.03 / 4.69

14.06 / 9.38

3.52 / 2.34

1.76 / 1.17

1100

2.375

7.42 / 4.95

14.84 / 9.90

3.71 / 2.47

1.86 / 1.24

Buck regulators SW1 to SW4 use 8 bits to set the output voltage.

• The VSWx_RUN[7:0] set the output voltage during the run mode.

• The VSWx_STBY[7:0] set the output voltage during the standby mode.

The default output voltage configuration for the run and the standby modes is loaded

from the OTP_VSWx[7:0] registers upon power up.

Table 43. SW1 to SW4 output voltage configuration

Set point

VSWx_RUN[7:0]

VSWx_STBY[7:0]

VSWxFB (V)

00000000

0.40000

00000001

0.40625

00000010

0.41250

00000011

0.41875

175

10101111

1.49375

176

10110000

1.50000

177

10110001

1.80000

178 to 255

10110010 to 11111111

Reserved

DVS operation is available for all voltage settings between 0.4 V to 1.5 V. However,

the SWx regulator is not intended to perform DVS transitions to or from the 1.8 V

configuration. In the event a voltage change is requested between any of the low voltage

MPF7100BVMA2ES Datasheet(PDF) 59 Page - NXP Semiconductors

MPF7100BVMA2ES Datasheet(HTML) 59 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL