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MPF7100BVMA2ES Datasheet(PDF) 55 Page - NXP Semiconductors |
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MPF7100BVMA2ES Datasheet(HTML) 55 Page - NXP Semiconductors |
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55 / 125 page  NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 55 / 125 Register Bit Description ABIST UV1 AB_SW3_UV Writing a 1 to this flag to clear the ABIST fault notification ABIST UV1 AB_SW4_UV Writing a 1 to this flag to clear the ABIST fault notification ABIST UV1 AB_SW5_UV Writing a 1 to this flag to clear the ABIST fault notification ABIST UV2 AB_LDO1_UV Writing a 1 to this flag to clear the ABIST fault notification ABIST UV2 AB_LDO2_UV Writing a 1 to this flag to clear the ABIST fault notification ABIST RUN AB_RUN Writing a 1 starts an ABIST on demand FSOB FLAGS FSOB_ASS_NOK Writing a 1 to this flag to clear the FSOB flag FSOB FLAGS FSOB_SFAULT_NOK Writing a 1 to this flag to clear the FSOB flag FSOB FLAGS FSOB_WDI_NOK Writing a 1 to this flag to clear the FSOB flag FSOB FLAGS FSOB_WDC_NOK Writing a 1 to this flag to clear the FSOB flag FSOB FLAGS FSOB_HFAULT_NOK Writing a 1 to this flag to clear the FSOB flag CTRL1 TMP_MON_EN Writing a 0 disables the thermal monitor, preventing the thermal interrupts and thermal shutdown event from being detected CTRL1 WDI_MODE Writing a 0 sets the WDI event to soft WD reset Writing a 1 sets the WDI event to hard WD reset CTRL1 VIN_OVLO_EN Writing a 0 disables the VIN overvoltage lockout monitor completely CTRL1 VIN_OVLO_SDWN Writing a 0 disables a shutdown event upon a VIN overvoltage condition (only interrupts are provided) CTRL1 WD_EN Writing a 0 disables the watchdog counter block CTRL1 WD_STBY_EN Writing a 0 disables the watchdog counter during the standby mode CTRL1 WDI_STBY_ACTIVE Writing a 0 disables the monitoring of WDI input during standby mode CTRL1 I2C_SECURE_EN Writing a 0 disables the I2C secure write mode VMONEN1 SW1VMON_EN Writing a 0 disables the OV/UV monitor for SW1 VMONEN1 SW2VMON_EN Writing a 0 disables the OV/UV monitor for SW2 VMONEN1 SW3VMON_EN Writing a 0 disables the OV/UV monitor for SW3 VMONEN1 SW4VMON_EN Writing a 0 disables the OV/UV monitor for SW4 VMONEN1 SW5VMON_EN Writing a 0 disables the OV/UV monitor for SW5 VMONEN2 LDO1VMON_EN Writing a 0 disables the OV/UV monitor for LDO1 VMONEN2 LDO2VMON_EN Writing a 0 disables the OV/UV monitor for LDO2 15 Functional blocks 15.1 Analog core and internal voltage references All regulators use the main band gap as the reference for the output voltage generations. The main band gap is also used as reference for the internal analog core and digital core supplies. The performance of the regulators is directly dependent on the performance of the band gap. |
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