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MPF7100BVMA2ES Datasheet(PDF) 25 Page - NXP Semiconductors

Part # MPF7100BVMA2ES
Description  7-channel power management integrated circuit for high performance applications
PDF  125 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPF7100BVMA2ES Datasheet(HTML) 25 Page - NXP Semiconductors

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NXP Semiconductors
PF7100
7-channel power management integrated circuit for high performance applications
PF7100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 9 March 2021
25 / 125
14.5 Power up
14.5.1 Power up events
Upon a power cycle (VIN > UVDET), the LPM_OFF bit is reset to 0, therefore the device
moves to the LP_Off state by default. The actual value of the LPM_OFF bit can be
changed during the run mode and is maintained until VIN crosses the UVDET threshold.
In either one of the Off modes, the PF7100 can be enabled by the following power up
events:
1. When OTP_PWRON_MODE = 0, PWRON pin is pulled high.
2. When OTP_PWRON_MODE = 1, PWRON pin experiences a high to low transition
and remains low for as long as the PWRON_DBNC timer.
A power up event is valid only if:
• VIN > UVDET
• VIN < VIN_OVLO (unless the OVLO is disabled or OTP_VIN_OVLO_SDWN = 0)
• Tj < thermal shutdown threshold
• TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0
14.5.2 Power up sequencing
The power up sequencer controls the time and order in which the voltage regulators and
other controlling I/O are enabled when going from the OFF mode into the run state.
The OTP_SEQ_TBASE[1:0] bits set the default timebase for the power up and power
down sequencer.
The SEQ_TBASE[1:0] bits can be modified during the system-on states in order to
change the sequencer timing during run/standby transitions as well as the power down
sequence.
Table 18. Power up timebase register
OTP bits
OTP_SEQ_TBASE[1:0]
Functional bits
SEQ_TBASE[1:0]
Sequencer timebase
(µs)
00
00
30
01
01
120
10
10
250
11
11
500
The power up sequence may include any of the following:
• Switching regulators
• LDO regulators
• PGOOD pin if programmed as a GPO
• RESETBMCU
The default sequence slot for each one of these signals is programmed via the OTP
configuration registers. And they can be modified in the functional I2C register map to
change the order in which the sequencer behaves during the run/standby transitions as
well as the power down sequence.



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