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MPF7100BVMA2ES Datasheet(PDF) 11 Page - NXP Semiconductors |
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MPF7100BVMA2ES Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 125 page  NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 11 / 125 13 State machine The PF7100 features a state of the art state machine for seamless processor interface. The state machine handles the IC startup, provides fault monitoring and reporting, and protects the IC and the system during fault conditions. Fault WD_Reset D Q O L R F K U J P M C E Z N S Fault POWER DOWN Turn-Off POWER DOWN 1. WD_FAIL_CNT = WD_MAX_CNT OR 2. PU_FAIL = True OR 3. FAULT_CNT = FAULT_MAX_CNT OR 4. Fault_Timer_Expired OR 5. Tj > TSD 1. PWRON = 0 OR 2. PWRON H to L && PWRON = 0 > TRESET OR 3. PMIC_OFF = 1 && 500us_Shutdown_timer_expired OR 4. VIN_OVLO_SDWN = 1 && VIN_OVLO detected * Output is enabled/asserted if it is programmed to do so by the OTP configuration Turn-off Power Up Sequence Off Modes Hard WD Reset Event System ON Power up regulators per OTP sequence PU_FAIL = True Power up failure BG_OK OTP_OK 20 MHz_OK FS_CNT++ Regulators off VSNVSx = On* FSOB = LOW* Fail self-test (ST_COUNT < 3) FS_CNT = FS_MAX_CNT && OTP_FS_BYPASS = 0 1. FS_CNT < FS_MAX_CNT OR 2. OTP_FS_BYPASS = 1 Regulators off FSOB = LOW* VSNVSx = On* TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0 VIN > UVDET V1P5D_POR V1P5A_POR VIN < UVDET CRITICAL FAILURE WD_FAIL_CNT++ RESETBMCU = HIGH Sys ON Sequence RUN Fau lt Sh utdo wn Fa il s elf -te sts (ST _C OU NT = 3 ) Tu rn- off ev en t Standby B A QPU_Off LP_Off Self- Test 2 ms delay OTP & Trim Load VSNVSx On* Fail-Safe State Fail-Safe Transition Power Down NO POWER ASIL-B only QM only 5. XFAILB = low && 20us delay (Only if OTP_XFAIL_EN = 1) Figure 6. State diagram Table 11 lists the conditions for the different state machine transitions. |
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