MPF7100BVMA2ES datasheet(80/125 Pages) NXP

80 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

80 / 125

The clock management provides clocking signals for the internal state machine, the

switching frequencies for the seven buck converters as well as the multiples of those

switching frequencies in order to enable phase shifting for multiple phase operations.

aaa-028068

DIVIDE

1 OR 6

INTERNAL

OSCILLATOR

20 MHz ± 20 % 16 to 24 MHz

SYNCIN

333 to 500 kHz

or 2 - 3 MHz

16 to 24 MHz

CLOCK MANAGEMENT BLOCK

416.67 kHz

333 kHz - 500 kHz

OUT

f1 + 45°

f1 + 90°

f1 + 135°

f1 + 180°

f1 + 225°

f1 + 270°

f1 + 315°

centered

DIVIDE

FREQUENCY

WATCHDOG

INTERNAL

OSCILLATOR

100 kHz ± 5 %

FSS_EN

FSS_RANGE

CKL_FRQ[3:0]

FSYNC_RANGE

OTP_SYNCIN_EN

100 kHz

system clock

MUX

SYNOUT_EN

PLL

X48

DIV 1

BY 8

DLY

I/O

SYNCOUT

Figure 32. Clock management architecture

15.7.1 Low frequency clock

Low power 100 kHz clock is provided for overall logic and digital control. Internal logic

and debounce timers are based on this 100 kHz clock.

15.7.2 High frequency clock

The PF7100 features a high frequency clock with nominal frequency of 20 MHz. Clock

frequency is programmable over a range of ±20 % via the CLK_FREQ[3:0] control bits.

15.7.3 Manual frequency tuning

The PF7100 features a manual frequency tuning to set the switching frequency of the

high frequency clock. The CLK_FREQ [3:0] bits allow a manual frequency tuning of the

high frequency clock from 16 MHz to 24 MHz.

If a frequency change of two or more steps is requested by a single I2C command, the

device performs a gradual frequency change passing through all steps in between with a

5.2 µs time between each frequency step. When the frequency reaches the programmed

value, the FREQ_RDY_I asserts the INTB pin, provided it is not masked.

When the internal clock is used as the main frequency for the power generation, an

internal frequency divider by 8 is used to generate the switching frequency for all the

buck regulators. Adjusting the frequency of the high frequency clock allows for manual

tuning of the switching frequencies for the buck regulators from 2.0 MHz to 3.0 MHz.

MPF7100BVMA2ES Datasheet(PDF) 80 Page - NXP Semiconductors

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