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MPF7100BVMA2ES Datasheet(PDF) 5 Page - NXP Semiconductors |
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MPF7100BVMA2ES Datasheet(HTML) 5 Page - NXP Semiconductors |
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5 / 125 page ![]() NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 5 / 125 7 Pinning information 7.1 Pinning aaa-034297 FSOB 36 RESETBMCU 35 PWRON 34 STANDBY 33 TBBEN 32 SW1FB 31 SW2FB 30 DGND 29 V1P5D 28 VIN 27 AGND 26 AMUX 25 WDI 1 SYNCOUT 2 EWARN 3 LDO2EN 4 SYNCIN 5 SW4FB 6 SW3FB EPAD 7 VDDOTP 8 VDDIO 9 SDA 10 SCL 11 SW5FB 12 Figure 4. Pin configuration for HVQFN48 7.2 Pin definitions Table 3. Pin definitions Pin number Symbol Application description Pin type Min Max Units 1 WDI Watchdog Input from MCU I −0.3 6.0 V 2 SYNCOUT Clock out pin for external part synchronization O −0.3 6.0 V 3 EWARN Early warning to MCU O −0.3 6.0 V 4 LDO2EN LDO2 enable pin I −0.3 6.0 V 5 SYNCIN External clock input pin for synchronization I −0.3 6.0 V 6 SW4FB Buck 4 output voltage feedback I −0.3 6.0 V 7 SW3FB Buck 3 output voltage feedback I −0.3 6.0 V 8 VDDOTP OTP selection input I −0.3 10 V 9 VDDIO I/O supply voltage. Connect to voltage rail between 1.6 V and 3.3 V. I −0.3 6.0 V 10 SDA I2C data signal I/O −0.3 6.0 V 11 SCL I2C clock signal I −0.3 6.0 V 12 SW5FB Buck 5 output voltage feedback I −0.3 6.0 V 13 XINTB External interrupt input I −0.3 6.0 V 14 NC1 Reserved — — — — 15 SW5IN Buck 5 input supply I −0.3 6.0 V |
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