MPF7100BVMA2ES datasheet(64/125 Pages) NXP

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NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

64 / 125

aaa-030480

VOUT

VIN (2.5 to 5.5 V)

SW1FB

1.0 µH

22 µF

x 8

4.7 µF

x 4

1.0 µH

QUAD PHASE

CONFIGURATION

SW1IN

SW2FB

SW2IN

SW2LX

SW3FB

SW3IN

SW3LX

SW4FB

SW4IN

SW4LX

SW1LX

1.0 µH

Figure 28. Quad phase configuration

15.3.3 Electrical characteristics

Table 50. Type 1 buck regulator electrical characteristics

All parameters are specified at TA = −40 °C to 125 °C for AEC-Q100 grade 1 device, all parameters are specified at TA =

−40 °C to 105 °C for AEC-Q100 grade 2 device, VIN = VSWxIN = UVDET to 5.5 V, VSWxFB = 1.0 V, ISWx = 500 mA, typical

external component values, fSW = 2.25 MHz, unless otherwise noted. Typical values are characterized at VIN = VSWxIN = 5.0

V, VSWxFB = 1.0 V, ISWx = 500 mA, and TA = 25 °C, unless otherwise noted.

Symbol

Parameter

[1] [2]

Min

Typ

Max

Unit

VSWxIN [3]

Operating functional input voltage

UVDET

—

5.5

VSWxACC

Output voltage accuracy

PWM mode

0.4 V ≤ VSWxFB < 0.8 V

0 ≤ ISWx ≤ 2.5 A

−10

—

VSWxACC

Output voltage accuracy

PWM mode

0.8 V ≤ VSWxFB ≤ 1.0 V

0 ≤ ISWx ≤ 2.5 A

−1.5

—

1.5

VSWxACC

Output voltage accuracy

PWM mode

1.0 V < VSWxFB ≤ 1.5 V

0 ≤ ISWx ≤ 2.5 A

−1.5

—

1.5

VSWxACC

Output voltage accuracy

PWM mode

VSWxFB = 1.8 V

0 ≤ ISWx ≤ 2.5 A

−1.5

—

1.5

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