MPF7100BVMA2ES datasheet(28/125 Pages) NXP

28 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

28 / 125

14.6 Power down

14.6.1 Turn off events

Turn off events may be requested by the MCU (non-PMIC fault related) or due to a

critical failure of the PMIC (hard fault condition).

The following are considered non-PMIC failure turn off events:

1. When OTP_PWRON_MODE = 0, the device starts a power down sequence when the

PWRON pin is pulled low.

2. When OTP_PWRON_MODE = 1, the device starts a power down sequence when

the PWRON pin sees a transition from high to low and remains low for longer than

TRESET.

3. When bit PMIC_OFF is set to 1, the device starts a 500 µs shutdown timer. When

the shutdown timer is started, the PF7100 sets the SDWN_I interrupt and asserts

the INTB pin provided it is not masked. At this point, the MCU can read the interrupt

and decide whether to continue with the turn off event or stop it in case it was sent by

mistake.

If the SDWN_I bit is cleared before the 500 µs shutdown timer is expired, the

shutdown request is canceled and the shutdown timer is reset; otherwise, if the

shutdown timer expires, the PF7100 starts a power down sequence.

The PMIC_OFF bit self-clears after SDWN_I flag is cleared.

4. When VIN_OVLO_EN = 1 and VIN_OVLO_SDWN = 1, and a VIN_OVLO event is

present.

Turn off events due to a hard fault condition:

1. If an OV, UV or ILIM condition is present long enough for the fault timer to expire.

2. In the event that an OV, UV or ILIM condition appears and clears cyclically, and the

FAULT_CNT[3:0] = FAULT_MAX_CNT[3:0].

3. If the watchdog fail counter is overflown, that is WD_EVENT_CNT = WD_MAX_CNT.

4. When Tj crosses the thermal shutdown threshold as the temperature rises.

When the PF7100 experiences a turn off event due to a hard fault condition, the device

passes through the fail-safe transition after regulators have been powered down.

14.6.2 Power down sequencing

During a power down sequence, output voltage regulators can be turned off in two

different modes as defined by the PWRDWN_MODE bit.

1. When PWRDWN_MODE = 0, the regulators power down in sequential mode.

2. When PWRDWN_MODE = 1, the regulators power down by groups.

During transition from run to standby, the power down sequencer is activated in the

corresponding mode. If any of the external regulators are turned off in the standby

configuration. If external regulators are not turned off during this transition, the power

down sequencer is bypassed and the transition happens at once (any associated DVS

transitions could still take time).

The PWRDN_I interrupt is set at the end of the transition from run to standby when the

last regulator has reached its final state, even if external regulators are not turned off

during this transition.

MPF7100BVMA2ES Datasheet(PDF) 28 Page - NXP Semiconductors

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