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MPF7100BVMA2ES Datasheet(PDF) 101 Page - NXP Semiconductors

Part # MPF7100BVMA2ES
Description  7-channel power management integrated circuit for high performance applications
PDF  125 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPF7100BVMA2ES Datasheet(HTML) 101 Page - NXP Semiconductors

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NXP Semiconductors
PF7100
7-channel power management integrated circuit for high performance applications
PF7100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 9 March 2021
101 / 125
AD
DR
Register Name
R/W
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
36
VMONEN2
R/SW
—
—
—
—
—
—
LDO2VMON_EN
LDO1VMON_EN
37
CTRL1
R/SW
VIN_OVLO_EN
VIN_OVLO_SDWN
WDI_MODE
TMP_MON_EN
WD_EN
WD_STBY_EN
WDI_STBY_ACTIVE —
38
CTRL2
R/W
VIN_OVLO_DBNC[1:0]
—
TMP_MON_AON
LPM_OFF
STANDBYINV
RUN_PG_GPO
STBY_PG_GPO
39
CTRL3
R/W
OV_DB[1:0]
UV_DB[1:0]
—
—
PMIC_OFF
INTB_TEST
3A
PWRUP CTRL
R/W
—
PWRDWN_MODE
PGOOD_PDGRP[1:0]
RESETBMCU_PDGRP[1:0]
SEQ_TBASE[1:0]
3C
RESETBMCU
PWRUP
R/W
RESETBMCU_SEQ[7:0]
3D
PGOOD PWRUP
R/W
PGOOD_SEQ[7:0]
3E
PWRDN DLY1
R/W
GRP4_DLY[1:0]
GRP3_DLY[1:0]
GRP2_DLY[1:0]
GRP1_DLY[1:0]
3F
PWRDN DLY2
R/W
—
—
—
—
—
—
RESETBMCU_DLY[1:0]
40
FREQ CTRL
R/W
SYNCOUT_EN
FSYNC_RANGE
FSS_EN
FSS_RANGE
CLK_FREQ[3:0]
42
PWRON
R/W
—
—
—
PWRON_DBNC [1:0]
PWRON_RST_EN
TRESET[1:0]
43
WD CONFIG
R/W
—
—
—
—
WD_DURATION[3:0]
44
WD CLEAR
R/W1C
—
—
—
—
—
—
—
WD_CLEAR
45
WD EXPIRE
R/W
—
WD_MAX_EXPIRE[2:0]
—
WD_EXPIRE_CNT[2:0]
46
WD COUNTER
R/W
WD_MAX_CNT [3:0]
WD_EVENT_CNT [3:0]
47
FAULT
COUNTER
R/W
FAULT_MAX_CNT[3:0]
FAULT_CNT [3:0]
49
FAULT TIMERS
R/W
—
—
—
—
TIMER_FAULT[3:0]
4A
AMUX
R/W
—
—
AMUX_EN
AMUX_SEL [4:0]
4D
SW1 CONFIG1
R/W
SW1_UV_
BYPASS
SW1_OV_BYPASS
SW1_ILIM_BYPASS SW1_UV_STATE
SW1_OV_STATE
SW1_ILIM_STATE
SW1_WDBYPASS
SW1_PG_EN
4E
SW1 CONFIG2
R/W
SW1_FLT_REN
SW1DVS_RAMP[1:0]
SW1ILIM[1:0]
SW1PHASE[2:0]
4F
SW1 PWRUP
R/W
SW1_SEQ[7:0]
50
SW1 MODE
R/W
—
—
SW1_PDGRP[1:0]
SW1_STBY_MODE[1:0]
SW1_RUN_MODE[1:0]
51
SW1 RUN VOLT
R/W
VSW1_RUN[7:0]
52
SW1 STBY VOLT
R/W
VSW1_STBY[7:0]
55
SW2 CONFIG1
R/W
SW2_UV_
BYPASS
SW2_OV_BYPASS
SW2_ILIM_BYPASS SW2_UV_STATE
SW2_OV_STATE
SW2_ILIM_STATE
SW2_WDBYPASS
SW2_PG_EN
56
SW2 CONFIG2
R/W
SW2_FLT_REN
SW2DVS_RAMP[1:0]
SW2ILIM[1:0]
SW2PHASE[2:0]
57
SW2 PWRUP
R/W
SW2_SEQ[7:0]
58
SW2 MODE1
R/W
—
—
SW2_PDGRP[1:0]
SW2_STBY_MODE[1:0]
SW2_RUN_MODE[1:0]
59
SW2 RUN VOLT
R/W
VSW2_RUN[7:0]
5A
SW2 STBY VOLT
R/W
VSW2_STBY[7:0]
5D
SW3 CONFIG1
R/W
SW3_UV_
BYPASS
SW3_OV_BYPASS
SW3_ILIM_BYPASS SW3_UV_STATE
SW3_OV_STATE
SW3_ILIM_STATE
SW3_WDBYPASS
SW3_PG_EN
5E
SW3 CONFIG2
R/W
SW3_FLT_REN
SW3DVS_RAMP[1:0]
SW3ILIM[1:0]
SW3PHASE[2:0]
5F
SW3 PWRUP
R/W
SW3_SEQ[7:0]
60
SW3 MODE1
R/W
—
SW3_VTTEN
SW3_PDGRP[1:0]
SW3_STBY_MODE[1:0]
SW3_RUN_MODE[1:0]
61
SW3 RUN VOLT
R/W
VSW3_RUN[7:0]
62
SW3 STBY VOLT
R/W
VSW3_STBY[7:0]
65
SW4 CONFIG1
R/W
SW4_UV_
BYPASS
SW4_OV_BYPASS
SW4_ILIM_BYPASS SW4_UV_STATE
SW4_OV_STATE
SW4_ILIM_STATE
SW4_WDBYPASS
SW4_PG_EN
66
SW4 CONFIG2
R/W
SW4_FLT_REN
SW4DVS_RAMP[1:0]
SW4ILIM[1:0]
SW4PHASE[2:0]
67
SW4 PWRUP
R/W
SW4_SEQ[7:0]
68
SW4 MODE1
R/W
—
—
SW4_PDGRP[1:0]
SW4_STBY_MODE[1:0]
SW4_RUN_MODE[1:0]
69
SW4 RUN VOLT
R/W
VSW4_RUN[7:0]
6A
SW4 STBY VOLT
R/W
VSW4_STBY[7:0]
7D
SW5 CONFIG1
R/W
SW5_UV_
BYPASS
SW5_OV_BYPASS
SW5_ILIM_BYPASS SW5_UV_STATE
SW5_OV_STATE
SW5_ILIM_STATE
SW5_WDBYPASS
SW5_PG_EN
7E
SW5 CONFIG2
R/W
SW5_FLT_REN —
—
SW5ILIM[1:0]
SW5PHASE[2:0]
7F
SW5 PWRUP
R/W
SW5_SEQ[7:0]
80
SW5 MODE1
R/W
—
—
SW5_PDGRP[1:0]
SW5_STBY_MODE[1:0]
SW5_RUN_MODE[1:0]
81
SW5 RUN VOLT
R/W
—
—
—
VSW5[4:0]



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