MPF7100BVMA2ES datasheet(104/125 Pages) NXP

104 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

104 / 125

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

OTP_ILIM_

BYPASS2

—

OTP_LDO2_

ILIMBYPASS

OTP_LDO1_

ILIMBYPASS

OTP_PROG_

IDH

—

OTP_PROG_ID11

OTP_PROG_ID10

OTP_PROG_ID9

OTP_PROG_ID8

OTP_PROG_

IDL

OTP_PROG_ID7

OTP_PROG_ID6

OTP_PROG_ID5

OTP_PROG_ID4

OTP_PROG_ID3

OTP_PROG_ID2

OTP_PROG_ID1

OTP_PROG_ID0

OTP_DEBUG1

—

OTP_BGMON_BYPASS

17 OTP/TBB and hardwire default configurations

The PF7100 supports OTP fuse bank configuration and a predefined hardwire

configuration to select the default power up configuration via the VDDOTP pin.

The default power up configuration is loaded into the functional I2C registers based on

the voltage on VDDOTP pin on register loading.

• If VDDOTP = GND, the device loads the configuration from the OTP mirror registers.

• If VDDOTP = V1P5D, the device loads the configuration from the default hardwire

configuration.

When OTP configuration is selected, the register loading occurs in two stages:

• In the first stage, the fuses are loaded in the OTP mirror registers each time VIN

crosses the UVDET threshold in the rising edge.

• At the second stage, data from the mirror registers are loaded into the functional I2C

registers for device operation.

When VDDOTP = GND, the mirror registers hold the default configuration to be used

on a power-on event. The mirror registers can be modified during the TBB mode to test

a custom power up configuration and/or burn the configuration into the OTP fuses to

generate a customized default power up configuration.

When VDDOTP = V1P5D, the I2C functional register are always loaded from the

hardwire configuration each time a default loading is required. Therefore, no TBB

operation is possible in this configuration.

In the event of a TRIM/OTP loading failure or a self-test failure, the corresponding fault

flag is set and any PWRUP event is ignored until the flags are cleared by writing a 1

during the QPU_OFF state.

The TRIM_NOK, OTP_NOK and STEST_NOK flags can only be written when the

TBBEN = V1P5D (in TBB mode). In normal operation, the TRIM_NOK, OTP_NOK and

STEST_NOK flags can only be read, but not cleared.

17.1 TBB (Try Before Buy) operation

The PF7100 allows temporary configuration (TBB) to debug or test a customized power

up configuration in the system. In order to access the TBB mode, the TBBEN pin should

be set high.

In this mode of operation, the device ignores the default value of the LPM_OFF bit and

moves into the QPU_Off state, regardless of the result of the self-test. However, the

actual result of the self-test is notified by the STEST_NOK flag.

• When the self-test is successful the STEST_NOK flag is set to 0

• When the self-test has failed, the STEST_NOK flag is set to 1

In the TBB mode, the following conditions are valid:

MPF7100BVMA2ES Datasheet(PDF) 104 Page - NXP Semiconductors

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