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MPF7100BVMA2ES Datasheet(PDF) 106 Page - NXP Semiconductors |
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MPF7100BVMA2ES Datasheet(HTML) 106 Page - NXP Semiconductors |
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106 / 125 page  NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 106 / 125 aaa-034306 LP_Off QPU_Off Power On Event Self-Test l2C POWER UP POWER OFF SYSTEM ON Mirror Registers FUSE LOAD Vin > UVDET OTP Config Hardwire Config I2C Register Map TBB Default Configuration l2C Register Map TBB Power up lf TBBEN = V1P5D (Limited Functionality) lf TBBEN = GND (Full Functionality) Configuration Modified TBB Configuration TBBEN = V1P5D VDDOTP = 0v I2C Register Map Mirror Registers Mirror Registers Figure 40. TBB operation diagram 17.2 OTP fuse programming A permanent OTP configuration is possible by burning the OTP fuses. OTP fuse burning is performed in the TBBEN mode during the QPU_Off state. Contact your NXP representative for detailed information on OTP fuse programming. 17.3 Default hardwire configuration If VDDOTP = V1P5D, the device loads the configuration from the default hardwire configuration directly into the corresponding I2C functional registers every time the registers need to be reloaded. |
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