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MPF7100BVMA2ES Datasheet(PDF) 108 Page - NXP Semiconductors

Part # MPF7100BVMA2ES
Description  7-channel power management integrated circuit for high performance applications
PDF  125 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPF7100BVMA2ES Datasheet(HTML) 108 Page - NXP Semiconductors

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NXP Semiconductors
PF7100
7-channel power management integrated circuit for high performance applications
PF7100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 9 March 2021
108 / 125
aaa-028077
LP_Off
QPU_Off
PWRON
event
PWRON
event
Self-Test
POWER UP
POWER OFF
SYSTEM ON
FUSE LOAD
Vin > UVDET
Default
Config
OTP
Config
I2C Register
Map
TBB Default
Configuration
Hardwire
Power up Configuration
lf TBBEN = V1P5D
(Limited Functionality)
lf TBBEN = GND
(Full Functionality)
TBBEN = V1P5D
· WDI disabled
· Watchdog Disabled
· l2C CRC disabled
· l2C Address = 0x08
· Access Miscellaneous
Debug flags
VDDOTP = V1P5D
I2C Register
Map
I2C Register
Map
Mirror
Registers
Mirror
Registers
Figure 41. Hardwire operation diagram
For simplicity, the default hardwire configuration in PF7100 is organized based on the
OTP register map as shown in Table 75.
Table 75. Default hardwire configuration
ADDR
Register name
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
Configuration
A0
OTP FSOB SELECT
0
0
0
0
0
0
0
0
Active Safe State disabled | FSOB pin not used
A1
OTP I2C
0
0
0
0
0
0
0
0
Secured I2C disabled | I2C CRC disabled | I2C address = 0x08
A2
OTP CTRL1
0
0
0
0
0
0
1
0
100us EWARN | Fail-safe State enabled | STANDBY active high | PGOOD indicator
| PG not Check on power up
A3
OTP CTRL2
0
0
0
0
0
1
0
1
FSS disabled | FSS Range = 5 % | XFAILB disabled | VIN_OVLO shutdown
disabled | VIN_OVLO enabled | VIN_OVLO debounce = 100 µs
A4
OTP CTRL3
0
0
0
0
0
0
0
1
VTT pulldown enabled | Single phase: SW5, SW4, SW3 | Dual phase: SW1/SW2



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