PIC16F7X7 datasheet(27/276 Pages) MICROCHIP

27 / 276 page

 2004 Microchip Technology Inc.

DS30498C-page 25

PIC16F7X7

2.2.2.5

PIR1 Register

The PIR1 register contains the individual flag bits for

the peripheral interrupts.

PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ADDRESS 0Ch)

Note:

Interrupt flag bits are set when an interrupt

condition occurs regardless of the state of its

corresponding enable bit or the Global Inter-

rupt Enable bit, GIE (INTCON<7>). User

software should ensure the appropriate inter-

rupt bits are clear prior to enabling an interrupt.

R/W-0

R-0

R/W-0

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

bit 7

bit 0

bit 7

PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)

= A read or a write operation has taken place (must be cleared in software)

= No read or write has occurred

Note:

PSPIF is reserved on 28-pin devices; always maintain this bit clear.

bit 6

ADIF: A/D Converter Interrupt Flag bit

= An A/D conversion is completed (must be cleared in software)

= The A/D conversion is not complete

bit 5

RCIF: AUSART Receive Interrupt Flag bit

= The AUSART receive buffer is full

= The AUSART receive buffer is empty

bit 4

TXIF: AUSART Transmit Interrupt Flag bit

= The AUSART transmit buffer is empty

= The AUSART transmit buffer is full

bit 3

SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit

= The SSP interrupt condition has occurred and must be cleared in software before returning

from the Interrupt Service Routine. The conditions that will set this bit are:

SPI:

A transmission/reception has taken place.

I2C Slave:

A transmission/reception has taken place.

I2C Master:

A transmission/reception has taken place. The initiated Start condition was completed by

the SSP module. The initiated Stop condition was completed by the SSP module. The

initiated Restart condition was completed by the SSP module.The initiated Acknowledge

condition was completed by the SSP module. A Start condition occurred while the SSP

module was Idle (multi-master system). A Stop condition occurred while the SSP module

was Idle (multi-master system).

= No SSP interrupt condition has occurred

bit 2

CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare mode:

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM mode:

Unused in this mode.

bit 1

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

= TMR2 to PR2 match occurred (must be cleared in software)

= No TMR2 to PR2 match occurred

bit 0

TMR1IF: TMR1 Overflow Interrupt Flag bit

= TMR1 register overflowed (must be cleared in software)

= TMR1 register did not overflow

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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