PIC16F7X7 datasheet(94/276 Pages) MICROCHIP

94 / 276 page

PIC16F7X7

DS30498C-page 92

 2004 Microchip Technology Inc.

The CCPR1H register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM

operation.

When the CCPR1H and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the CCP1 pin is cleared.

The maximum PWM resolution (bits) for a given PWM

frequency is given by the formula:

EQUATION 9-3:

9.6.3

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

Set the PWM period by writing to the PR2 register.

Set the PWM duty cycle by writing to the

CCPR1L register and CCP1CON<5:4> bits.

Make the CCP1 pin an output by clearing the

TRISC<2> bit.

Set the TMR2 prescale value and enable Timer2

by writing to T2CON.

Configure the CCP1 module for PWM operation.

TABLE 9-4:

EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

TABLE 9-5:

REGISTERS ASSOCIATED WITH PWM AND TIMER2

Note:

If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be

cleared.

log

(

FPWM

log(2)

FOSC

)

bits

Resolution

PWM Frequency

1.22 kHz

4.88 kHz

19.53 kHz

78.12 kHz

156.3 kHz

208.3 kHz

Timer Prescale (1, 4, 16)

PR2 Value

0xFF

0x3F

0x1F

0x17

Maximum Resolution (bits)

6.6

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

Resets

0Bh,8Bh,

10Bh,18Bh

INTCON

GIE

PEIE

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

0Ch

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF 0000 0000 0000 0000

0Dh

PIR2

OSFIF

CMIF

LVDIF

—

BCLIF

—

CCP3IF

CCP2IF

000- 0-00 000- 0-00

8Ch

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE 0000 0000 0000 0000

8Dh

PIE2

OSFIE

CMIE

LVDIE

—

BCLIE

—

CCP3IE

CCP2IE 000- 0-00 000- 0-00

87h

TRISC

PORTC Data Direction Register

1111 1111 1111 1111

11h

TMR2

Timer2 Module Register

0000 0000 0000 0000

92h

PR2

Timer2 Period Register

1111 1111 1111 1111

12h

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

15h

CCPR1L

Capture/Compare/PWM Register 1 (LSB)

xxxx xxxx uuuu uuuu

16h

CCPR1H

Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx uuuu uuuu

17h

CCP1CON

—

CCP1X

CCP1Y

CCP1M3

CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

1Bh

CCPR2L

Capture/Compare/PWM Register 2 (LSB)

xxxx xxxx uuuu uuuu

1Ch

CCPR2H

Capture/Compare/PWM Register 2 (MSB)

xxxx xxxx uuuu uuuu

1Dh

CCP2CON

—

CCP2X

CCP2Y

CCP2M3

CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

95h

CCPR3L

Capture/Compare/PWM Register 3 (LSB)

xxxx xxxx uuuu uuuu

96h

CCPR3H

Capture/Compare/PWM Register 3 (MSB)

xxxx xxxx uuuu uuuu

97h

CCP3CON

—

CCP3X

CCP3Y

CCP3M3

CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000

Legend:

= unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.

Note

Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear.

PIC16F7X7 Datasheet(PDF) 94 Page - Microchip Technology

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