PIC16F7X7 datasheet(91/276 Pages) MICROCHIP

91 / 276 page

 2004 Microchip Technology Inc.

DS30498C-page 89

PIC16F7X7

9.4

Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 register when an event occurs

on pin RC2/CCP1. An event is defined as one of the

following and is configured by CCPxCON<3:0>:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

An event is selected by control bits, CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the inter-

rupt request flag bit, CCP1IF (PIR1<2>), is set. The

interrupt flag must be cleared in software. If another

capture occurs before the value in register CCPR1 is

read, the old captured value is overwritten by the new

captured value.

9.4.1

CCP PIN CONFIGURATION

In Capture mode, the RC2/CCP1 pin should be

configured as an input by setting the TRISC<2> bit.

FIGURE 9-1:

CAPTURE MODE

OPERATION BLOCK

DIAGRAM

9.4.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode for the CCP module to use the

capture feature. In Asynchronous Counter mode, the

capture operation may not work.

9.4.3

SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit,

CCP1IE (PIE1<2>), clear to avoid false interrupts and

should clear the flag bit, CCP1IF, following any such

change in operating mode.

9.4.4

CCP PRESCALER

There are four prescaler settings specified by bits,

CCP1M3:CCP1M0. Whenever the CCP module is

turned off, or the CCP module is not in Capture mode,

the prescaler counter is cleared. Any Reset will clear

the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared, therefore, the first capture may be from

non-zero

prescaler.

Example 9-1

shows

the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 9-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

9.5

Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RC2/CCP1 pin is:

• Driven high

•Driven low

• Remains unchanged

The action on the pin is based on the value of control

bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time, interrupt flag bit CCP1IF is set.

FIGURE 9-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

Note:

If the RC2/CCP1 pin is configured as an

output, a write to the port can cause a

capture condition.

CCPR1H

CCPR1L

TMR1H

TMR1L

Set Flag bit CCP1IF

(PIR1<2>)

Capture

Enable

Q’s

CCP1CON<3:0>

RC2/CCP1

Prescaler

÷ 1, 4, 16

and

Edge Detect

CLRF

CCP1CON

;Turn CCP module off

MOVLW

NEW_CAPT_PS

;Load the W reg with

;the new prescaler

;move value and CCP ON

MOVWF

CCP1CON

;Load CCP1CON with this

;value

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set Flag bit CCP1IF

(PIR1<2>)

Match

RC2/CCP1

TRISC<2>

CCP1CON<3:0>

Mode Select

Output Enable

Special Event Trigger will:

•

clear TMR1H and TMR1L registers

•

NOT set interrupt flag bit, TMR1IF (PIR1<0>)

•

(for CCP2 only) set the GO/DONE bit (ADCON0<2>)

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