PIC16F7X7 datasheet(92/276 Pages) MICROCHIP

92 / 276 page

PIC16F7X7

DS30498C-page 90

 2004 Microchip Technology Inc.

9.5.1

CCP PIN CONFIGURATION

The user must configure the RC2/CCP1 pin as an

output by clearing the TRISC<2> bit.

9.5.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

9.5.3

SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen, the

CCP1 pin is not affected. The CCP1IF or CCP2IF bit is

set, causing a CCP interrupt (if enabled).

9.5.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

The special event trigger output of CCP2 resets the

TMR1 register pair and starts an A/D conversion (if the

A/D module is enabled).

TABLE 9-3:

REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1

Note:

Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to

the default low level. This is not the

PORTC I/O data latch.

Note:

The special event trigger from the CCP1

and CCP2 modules will not set interrupt

flag bit, TMR1IF (PIR1<0>).

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

Resets

0Bh,8Bh,

10Bh,18Bh

INTCON

GIE

PEIE

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

0Ch

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF 0000 0000 0000 0000

0Dh

PIR2

OSFIF

CMIF

LVDIF

—BCLIF

—

CCP3IF

CCP2IF 000- 0-00 000- 0-00

8Ch

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE 0000 0000 0000 0000

8Dh

PIE2

OSFIE

CMIE

LVDIE

—BCLIE

—CCP3IE

CCP2IE 000- 0-00 000- 0-00

87h

TRISC

PORTC Data Direction Register

1111 1111 1111 1111

0Eh

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

0Fh

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

10h

T1CON

—

T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu

15h

CCPR1L

Capture/Compare/PWM Register 1 (LSB)

xxxx xxxx uuuu uuuu

16h

CCPR1H

Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx uuuu uuuu

17h

CCP1CON

—

CCP1X

CCP1Y

CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

1Bh

CCPR2L

Capture/Compare/PWM Register 2 (LSB)

xxxx xxxx uuuu uuuu

1Ch

CCPR2H

Capture/Compare/PWM Register 2 (MSB)

xxxx xxxx uuuu uuuu

1Dh

CCP2CON

—

CCP2X

CCP2Y

CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

95h

CCPR3L

Capture/Compare/PWM Register 3 (LSB)

xxxx xxxx uuuu uuuu

96h

CCPR3H

Capture/Compare/PWM Register 3 (MSB)

xxxx xxxx uuuu uuuu

97h

CCP3CON

—

CCP3X

CCP3Y

CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000

Legend:

= unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.

Note

The PSP is not implemented on the PIC16F737/767 devices; always maintain these bits clear.

PIC16F7X7 Datasheet(PDF) 92 Page - Microchip Technology

PIC16F7X7 Datasheet(HTML) 92 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL