JS48F4400P0P3C0 datasheet(112/139 Pages) NUMONYX

112 / 139 page

Numonyx™ StrataFlash® Cellular Memory (M18)

Datasheet

April 2008

112

309823-10

13h

Primary vendor command set and control interface ID code.

16-bit ID code for vendor-specified algorithms.

--00

--02

15h

Extended Query Table primary algorithm address.

--0A

--01

17h

Alternate vendor command set and control interface ID code.

0000h means no second vendor-specified algorithm exists.

--00

19h

Secondary algorithm Extended Query Table address. 0000h

means none exists.

--00

Table 52: CFI Identification (Sheet 2 of 2)

Offset

Length

Description

Address

Hex Code

Value

Table 53: System Interface Information (Sheet 1 of 2)

Offset

Length

Description

Address

Hex Code

Value

1Bh

VCC logic supply minimum

program/erase voltage.

bits 0-3 BCD 100 mV

bits 4-7 BCD volts

--17

1.7 V

1Ch

VCC logic supply maximum

program/erase voltage.

bits 0-3 BCD 100 mV

bits 4-7 BCD volts

--20

2.0 V

1Dh

VPP [programming] supply

minimum program/erase voltage.

bits 0-3 BCD 100 mV

bits 4-7 hex volts

--85

8.5 V

1Eh

VPP [programming] supply

maximum program/erase

voltage.

bits 0-3 BCD 100 mV

bits 4-7 hex volts

--95

9.5 V

1Fh

“n” such that typical single word

program timeout = 2n µs.

--06

64 µs

20h

“n” such that typical full buffer

write timeout = 2n µs.

--0B (256, 512 Mbit - 90 nm;

1024 Mbit - 65 nm)

--0A (128. 256, 512 Mbit -

65 nm)

2048 µs (256, 512 Mbit -

90 nm; 1024 Mbit - 65

nm)

1024 µs (128. 256, 512

Mbit - 65 nm)

21h

“n” such that typical block erase

timeout = 2n ms.

--0A

1 s

22h

“n” such that typical full chip

erase timeout = 2n ms.

--00

23h

“n” such that maximum word

program timeout = 2n times

typical.

--02

256 µs

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