XC2230L datasheet(30/112 Pages) INFINEON

30 / 112 page

XC2230L, XC2234L

XC2000 Family / Econo Line

Functional Description

Data Sheet

V1.3, 2015-02

Functional Description

The architecture of the XC223[04]L combines advantages of RISC, CISC, and DSP

processors with an advanced peripheral subsystem in a well-balanced design. On-chip

memory blocks allow the design of compact systems-on-silicon with maximum

performance suited for computing, control, and communication.

The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data

SRAM) and the generic peripherals are connected to the CPU by separate high-speed

buses. Another bus, the LXBus, connects additional on-chip resources and external

resources (see Figure 3). This bus structure enhances overall system performance by

enabling the concurrent operation of several subsystems of the XC223[04]L.

The block diagram gives an overview of the on-chip components and the advanced

internal bus structure of the XC223[04]L.

Figure 3

Block Diagram

DPRAM

CPU

ADC0

Module

8-/10- /

12 -Bit

RTC

MCHK

Interrupt & PEC

LXBUS

Controller

DSRAM

System Functions

Clock, Reset, Power

Control

OCDS

Debug Support

Interrupt Bus

Analog and Digital General Purpose IO (GPIO) Ports

MC_L- SERIES_BLOCKDIAGRAM

GPT

Timers

CC2

Module

Chan.

WWD

Multi

CAN

CCU6 x

Modules

3+1

Chan.

each

USICx

Modules

Chan.

each

PSRAM

Flash Memory

MAC Unit

MPU

XC2230L Datasheet(PDF) 30 Page - Infineon Technologies AG

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