XC2230L datasheet(38/112 Pages) INFINEON

38 / 112 page

XC2230L, XC2234L

XC2000 Family / Econo Line

Functional Description

Data Sheet

V1.3, 2015-02

(branching to a dedicated vector table location). The occurrence of a hardware trap is

also indicated by a single bit in the trap flag register (TFR). Unless another higher-priority

trap service is in progress, a hardware trap will interrupt any ongoing program execution.

In turn, hardware trap services can normally not be interrupted by standard or PEC

interrupts.

Depending on the package option up to 3 External Service Request (ESR) pins are

provided. The ESR unit processes their input values and allows to implement user

controlled trap functions (System Requests SR0 and SR1). In this way reset, wakeup

and power control can be efficiently realized.

Software interrupts are supported by the ‘TRAP’ instruction in combination with an

individual trap (interrupt) number. Alternatively to emulate an interrupt by software a

program can trigger interrupt requests by writing the Interrupt Request (IR) bit of an

interrupt control register.

3.6

On-Chip Debug Support (OCDS)

The On-Chip Debug Support system built into the XC223[04]L provides a broad range

of debug and emulation features. User software running on the XC223[04]L can be

debugged within the target system environment.

The OCDS is controlled by an external debugging device via the debug interface. This

consists of the 2-pin Device Access Port (DAP) or of the 1-pin Single Pin DAP (SPD) or

of the JTAG port conforming to IEEE-1149. The debug interface can be completed with

an optional break interface.

The debugger controls the OCDS with a set of dedicated registers accessible via the

debug interface (SPD, DAP or JTAG). In addition the OCDS system can be controlled

by the CPU, e.g. by a monitor program. An injection interface allows the execution of

OCDS-generated instructions by the CPU.

Multiple breakpoints can be triggered by on-chip hardware, by software, or by an

external trigger input. Single stepping is supported, as is the injection of arbitrary

instructions and read/write access to the complete internal address space. A breakpoint

trigger can be answered with a CPU halt, a monitor call, a data transfer, or/and the

activation of an external signal.

Tracing of data can be obtained via the debug interface, or via the external bus interface

for increased performance.

Tracing of program execution is supported by the XC2000 Family emulation device.

The SPD interface uses one interface signal, DAP interface uses two interface signals,

the JTAG interface uses four interface signals, to communicate with external circuitry.

The debug interface can be amended with two optional break lines.

XC2230L Datasheet(PDF) 38 Page - Infineon Technologies AG

XC2230L Datasheet(HTML) 38 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL