XC2230L datasheet(33/112 Pages) INFINEON

33 / 112 page

XC2230L, XC2234L

XC2000 Family / Econo Line

Functional Description

Data Sheet

V1.3, 2015-02

6 Kbytes of on-chip Data SRAM (DSRAM) are used for storage of general user data.

The DSRAM is accessed via a separate interface and is optimized for data access.

2 Kbytes of on-chip Dual-Port RAM (DPRAM) provide storage for user-defined

variables, for the system stack, and for general purpose register banks. A register bank

can consist of up to 16 word-wide (R0 to R15) and/or byte-wide (RL0, RH0, …, RL7,

RH7) General Purpose Registers (GPRs).

The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR,

any location in the DPRAM is bit addressable.

1024 bytes (2

× 512 bytes) of the address space are reserved for the Special Function

used to control and monitor functions of the different on-chip units. Unused SFR

addresses are reserved for future members of the XC2000 Family. In order to ensure

upward compatibility they should either not be accessed or written with zeros.

The on-chip Flash memory stores code, constant data, and control data. The

160 Kbytes of on-chip Flash memory consist of 1 module of 32 Kbytes (preferably for

data storage) and 1 module of 128 Kbytes. Each module is organized in 4-Kbyte sectors.

The uppermost 4-Kbyte sector of segment 0 (located in Flash module 0) is used

internally to store operation control parameters and protection information.

Each sector can be separately write protected

1), erased and programmed (in blocks of

128 Bytes). The complete Flash area can be read-protected. A user-defined password

sequence temporarily unlocks protected areas. The Flash modules combine 128-bit

read access with protected and efficient writing algorithms for programming and erasing.

Dynamic error correction provides extremely high read data security for all read access

operations. Access to different Flash modules can be executed in parallel.

For Flash parameters, please see Section 4.6.

Memory Content Protection

The contents of on-chip memories can be protected against soft errors (induced e.g. by

radiation) by activating the parity mechanism or the Error Correction Code (ECC).

The parity mechanism can detect a single-bit error and prevent the software from using

incorrect data or executing incorrect instructions.

The ECC mechanism can detect and automatically correct single-bit errors. This

supports the stable operation of the system.

It is strongly recommended to activate the ECC mechanism wherever possible because

this dramatically increases the robustness of an application against such soft errors.

1) To save control bits, sectors are clustered for protection purposes, they remain separate for

programming/erasing.

XC2230L Datasheet(PDF) 33 Page - Infineon Technologies AG

XC2230L Datasheet(HTML) 33 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL