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XC2230L Datasheet(PDF) 92 Page - Infineon Technologies AG |
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XC2230L Datasheet(HTML) 92 Page - Infineon Technologies AG |
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92 / 112 page  XC2230L, XC2234L XC2000 Family / Econo Line Electrical Parameters Data Sheet 88 V1.3, 2015-02 4.7.3 External Clock Input Parameters These parameters specify the external clock generation for the XC223[04]L. The clock can be generated in two ways: • By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2. • By supplying an external clock signal. This clock signal can be supplied either to pin XTAL1 (core voltage domain) or to pin CLKIN1 (IO voltage domain). If connected to CLKIN1, the input signal must reach the defined input levels V IL and VIH. If connected to XTAL1, a minimum amplitude V AX1 (peak-to-peak voltage) is sufficient for the operation of the on-chip oscillator. Note: The given clock timing parameters ( t 1 … t4) are only valid for an external clock input signal. Note: Operating Conditions apply. Table 29 External Clock Input Characteristics Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Oscillator frequency f OSC SR 4 − 40 MHz Input= Clock Signal 4 − 16 MHz Input= Crystal or Resonator XTAL1 input current absolute value | I IL| CC −− 20 μA Input clock high time t 1 SR 6 −− ns Input clock low time t 2 SR 6 −− ns Input clock rise time t 3 SR − 88 ns Input clock fall time t 4 SR − 88 ns Input voltage amplitude on XTAL1 1) 1) The amplitude voltage V AX1 refers to the offset voltage VOFF. This offset voltage must be stable during the operation and the resulting voltage peaks must remain within the limits defined by V IX1. V AX1 SR 0.3 x V DDIM −− V f OSC≥ 4MHz; f OSC≤ 16 MHz 0.4 x V DDIM −− V f OSC≥ 16 MHz; f OSC≤ 25 MHz 0.5 x V DDIM −− V f OSC≥ 25 MHz; f OSC≤ 40 MHz Input voltage range limits for signal on XTAL1 V IX1 SR -1.7 + V DDIM − 1.7 V 2) |
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