XC2230L datasheet(7/112 Pages) INFINEON

7 / 112 page

XC2230L, XC2234L

XC2000 Family / Econo Line

Summary of Features

Data Sheet

V1.3, 2015-02

16/32-Bit Single-Chip Microcontroller

with 32-Bit Performance

XC223[04]L (XC2000 Family)

Summary of Features

For a quick overview and easy reference, the features of the XC223[04]L are

summarized here.

•

High-performance CPU with five-stage pipeline and MPU

– 12.5 ns instruction cycle @ 80 MHz CPU clock (single-cycle execution)

– One-cycle 32-bit addition and subtraction with 40-bit result

– One-cycle multiplication (16

× 16 bit)

– Background division (32 / 16 bit) in 21 cycles

– One-cycle multiply-and-accumulate (MAC) instructions

– Enhanced Boolean bit manipulation facilities

– Zero-cycle jump execution

– Additional instructions to support HLL and operating systems

– Register-based design with multiple variable register banks

– Fast context switching support with two additional local register banks

– 16 Mbytes total linear address space for code and data

– 1,024 Bytes on-chip special function register area (C166 Family compatible)

– Integrated Memory Protection Unit (MPU)

•

Interrupt system with 16 priority levels providing 64 interrupt nodes

– Selectable external inputs for interrupt generation and wake-up

– Fastest sample-rate 12.5 ns

•

Eight-channel interrupt-driven single-cycle data transfer with

Peripheral Event Controller (PEC), 24-bit pointers cover total address space

•

Clock generation from internal or external clock sources,

using on-chip PLL or prescaler

•

Hardware CRC-Checker with Programmable Polynomial to Supervise On-Chip

Memory Areas

•

On-chip memory modules

– 2 Kbytes on-chip dual-port RAM (DPRAM)

– 6 Kbytes on-chip data SRAM (DSRAM)

– 4 Kbytes on-chip program/data SRAM (PSRAM)

– Up to 160 Kbytes on-chip program memory (Flash memory)

– Memory content protection through Error Correction Code (ECC) for Flash

memory and through parity for RAMs

XC2230L Datasheet(PDF) 7 Page - Infineon Technologies AG

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