XC2230L datasheet(55/112 Pages) INFINEON

55 / 112 page

XC2230L, XC2234L

XC2000 Family / Econo Line

Functional Description

Data Sheet

V1.3, 2015-02

When clocked by

SYS = 80 MHz, time intervals between 12.5 ns and 13.4 s can be

monitored.

When clocked by

WU = 500 kHz, time intervals between 2.0 µs and 2147.5 s can be

monitored.

The default Watchdog Timer interval after power-up is 0.13 s (@

WU = 500 kHz).

3.16

Clock Generation

The Clock Generation Unit can generate the system clock signal

SYS for the XC223[04]L

from a number of external or internal clock sources:

•

External clock signals with pad voltage or core voltage levels

•

External crystal or resonator using the on-chip oscillator

•

On-chip clock source for operation without crystal/resonator

•

Wake-up clock (ultra-low-power) to further reduce power consumption

The programmable on-chip PLL with multiple prescalers generates a clock signal for

maximum system performance from standard crystals, a clock input signal, or from the

on-chip clock source. See also Section 4.7.2.

The Oscillator Watchdog (OWD) generates an interrupt if the crystal oscillator frequency

falls below a certain limit or stops completely. In this case, the system can be supplied

with an emergency clock to enable operation even after an external clock failure.

All available clock signals can be output on the EXTCLK pin.

XC2230L Datasheet(PDF) 55 Page - Infineon Technologies AG