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XC2230L Datasheet(PDF) 31 Page - Infineon Technologies AG |
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XC2230L Datasheet(HTML) 31 Page - Infineon Technologies AG |
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31 / 112 page  XC2230L, XC2234L XC2000 Family / Econo Line Functional Description Data Sheet 27 V1.3, 2015-02 3.1 Memory Subsystem and Organization The memory space of the XC223[04]L is configured in the von Neumann architecture. In this architecture all internal and external resources, including code memory, data memory, registers and I/O ports, are organized in the same linear address space. Table 8 XC223[04]L Memory Map 1) Address Area Start Loc. End Loc. Area Size 2) Notes IMB register space FF’FF00 H FF’FFFF H 256 bytes Reserved F0’0000 H FF’FEFF H < 1 Mbyte Minus IMB registers. Reserved for EPSRAM E8’1000 H EF’FFFF H 508 Kbytes Mirrors EPSRAM Emulated PSRAM E8’0000 H E8’0FFF H up to 4 Kbytes With Flash timing. Reserved for PSRAM E0’1000 H E7’FFFF H 508 Kbytes Mirrors PSRAM PSRAM E0’0000 H E0’0FFF H up to 4 Kbytes Program SRAM. Reserved for Flash C4’8000 H DF’FFFF H 1760 Kbytes Flash 1 C4’0000 H C4’7FFF H 32 Kbytes Reserved for Flash C2’1000 H C3’FFFF H 124 Kbytes Flash 0 C0’0000 H C2’0FFF H 132 Kbytes 3) External memory area 40’0000 H BF’FFFF H 8 Mbytes External IO area 4) 21’0000 H 3F’FFFF H 1984 Kbytes Reserved 20’B800 H 20’FFFF H 18 Kbytes USIC0-1 alternate regs. 20’B000 H 20’B7FF H 2 Kbytes Accessed via LXBus Controller MultiCAN alternate regs. 20’8000 H 20’AFFF H 12 Kbytes Accessed via LXBus Controller Reserved 20’5000 H 20’7FFF H 12 Kbytes USIC0-1 registers 20’4000 H 20’4FFF H 4 Kbytes Accessed via LXBus Controller MultiCAN registers 20’0000 H 20’3FFF H 16 Kbytes Accessed via LXBus Controller External memory area 01’0000 H 1F’FFFF H 1984 Kbytes SFR area 00’FE00 H 00’FFFF H 0.5 Kbytes Dual-port RAM (DPRAM) 00’F600 H 00’FDFF H 2 Kbytes Reserved for DPRAM 00’F200 H 00’F5FF H 1 Kbytes |
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