PIC16F7X7 datasheet(109/276 Pages) MICROCHIP

109 / 276 page

 2004 Microchip Technology Inc.

DS30498C-page 107

PIC16F7X7

In 10-bit Address mode, two address bytes need to be

received by the slave. The five Most Significant bits

(MSbs) of the first address byte specify if this is a 10-bit

address. Bit R/W (SSPSTAT<2>) must specify a write

so the slave device will receive the second address

byte. For a 10-bit address, the first byte would equal

‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two

MSbs of the address. The sequence of events for

10-bit address is as follows, with steps 7 through 9 for

the slave-transmitter:

Receive first (high) byte of address (bits SSPIF,

BF and UA (SSPSTAT<1>) are set).

Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

Receive second (low) byte of address (bits

SSPIF, BF and UA are set).

Update the SSPADD register with the first (high)

byte of address. If match releases SCL line, this

will clear bit UA.

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

Receive Repeated Start condition.

Receive first (high) byte of address (bits SSPIF

and BF are set).

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

10.4.3.2

Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register and the SDA line is held low

(ACK).

When the address byte overflow condition exists, then

the no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF (SSPSTAT<0>) is

set or bit SSPOV (SSPCON<6>) is set.

An MSSP interrupt is generated for each data transfer

byte. Flag bit, SSPIF (PIR1<3>), must be cleared in

software. The SSPSTAT register is used to determine

the status of the byte.

If SEN is enabled (SSPCON<0> = 1), RC3/SCK/SCL

will be held low (clock stretch) following each data

transfer. The clock must be released by setting bit,

CKP (SSPCON<4>).

See

Section 10.4.4

“Clock

Stretching” for more detail.

10.4.3.3

Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is loaded

into the SSPBUF register. The ACK pulse will be sent on

the ninth bit and pin RC3/SCK/SCL is held low regard-

less of SEN (see Section 10.4.4 “Clock Stretching”

for more detail). By stretching the clock, the master will

be unable to assert another clock pulse until the slave is

done preparing the transmit data. The transmit data

must be loaded into the SSPBUF register, which also

loads the SSPSR register. Then pin RC3/SCK/SCL

should be enabled by setting bit CKP (SSPCON<4>).

The eight data bits are shifted out on the falling edge of

the SCL input. This ensures that the SDA signal is valid

during the SCL high time (Figure 10-9).

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCL input pulse. If the SDA

line is high (not ACK), then the data transfer is com-

plete. In this case, when the ACK is latched by the

slave, the slave logic is reset (resets SSPSTAT regis-

ter) and the slave monitors for another occurrence of

the Start bit. If the SDA line was low (ACK), the next

transmit data must be loaded into the SSPBUF register.

Again, pin RC3/SCK/SCL must be enabled by setting

bit CKP.

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared in software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

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