LMP90100MHESLASHNOPB datasheet(23/69 Pages) TI1

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VIN2

VIN4*

VIN3*

VREFN1

VIN6/VREFP2

ADC

VREFP1

VIN0

VIN5*

VIN1

VIN7/VREFN2

VINP

VINN

BUFF

FGA

* VIN3, VIN4, VIN5 are only available for LMP90100 and LMP90099

LMP90100

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SNAS510P – JANUARY 2011 – REVISED MARCH 2013

Figure 35. Simplified VIN Circuitry

Selectable Gains (FGA & PGA)

LMP90xxx provides two types of gain amplifiers: a fixed gain amplifier (FGA) and a programmable gain amplifier

(PGA). FGA has a fixed gain of 16x or it can be bypassed, while the PGA has programmable gain settings of 1x,

2x, 4x, or 8x.

Total gain is defined as FGA x PGA. Thus, LMP90xxx provides gain settings of 1x, 2x, 4x, 8x, 16x, 32x, 64x, or

128x with true continuous background calibration.

The gain is channel specific, which means that one channel can have one gain, while another channel can have

the same or a different gain.

The gain can be selected by programming the CHx_CONFIG: GAIN_SEL bits.

Buffer (BUFF)

There is an internal unity gain buffer that can be included or excluded from the signal path. Including the buffer

provides a high input impedance but increases the power consumption.

When gain

≥ 16, the buffer is automatically included in the signal path. When gain < 16, including or excluding

the buffer from the signal path can be done by programming the CHX_CONFIG: BUF_EN bit.

Internal/External CLK Selection

LMP90xxx allows two clock options: internal CLK or external CLK (crystal (XTAL) or clock source).

There is an “External Clock Detection” mode, which detects the external XTAL if it is connected to XOUT and

XIN. When operating in this mode, the LMP90xxx shuts off the internal clock to reduce power consumption.

Below is a flow chart to help set the appropriate clock registers.

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