LMP90100MHESLASHNOPB datasheet(41/69 Pages) TI1

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1/ODR

Sampling CH0

Sampling CH1

SDO

LSB

Reading

ADC_DOUT of CH0

Reading

SPI_CRC_DAT

LSB

MSB

LSB

Reading

ADC_DOUT of CH1

Reading

SPI_CRC_DAT

LSB

MSB

LMP90100

www.ti.com

SNAS510P – JANUARY 2011 – REVISED MARCH 2013

Table 7. Data First Mode Transactions

Bit[7]

Bits[6:5]

Bit[4]

Bits[3:0]

Data Bytes

Enable Data First

1010

None

Mode Instruction

Disable Data First

1011

None

Mode Instruction

Read Mode Status

1111

One

Transaction

Note that while being in the data first mode, once the data bytes in the data only read transaction are sent out,

the device is ready to start on any normal (non-data-only) transaction including the Disable Data First Mode

Instruction. The current status of the data first mode (enabled/disabled status) can be read back using the Read

Mode Status Transaction. This transaction consists of the Read Mode Status Instruction followed by a single

data byte (driven by the device). The data first mode status is available on bit [1] of this data byte.

The data only read transaction allows reading up to eight consecutive registers, starting from any start address.

Usually, the start address will be the address of the most significant byte of conversion data, but it could just as

well be any other address. The start address and number of bytes to be read during the data only read

transaction can be programmed using the DATA_ONLY_1 AND DATA_ONLY_2 registers respectively.

The upper register address is unaffected by a data only read transaction. That is, it retains its setting even after

encountering a data only transaction. The data only transaction uses its own address (including the upper

address) from the DATA_ONLY_1 register. When in the data first mode, the SCLK must stop high before

entering the Data Only Read Transaction; this transaction should be completed before the next scheduled

DRDYB deassertion.

Cyclic Redundancy Check (CRC)

CRC can be used to ensure integrity of data read from LMP90xxx. To enable CRC, set EN_CRC high. Once

CRC is enabled, the CRC value is calculated and stored in SPI_CRC_DAT so that the master device can

periodically read for data comparison. Conveniently, the SPI_CRC_DAT register address is located next to the

ADC_DOUT register address so that the CRC value can be easily read as part of the data set. The CRC is

automatically reset when CSB or DRDYB is deasserted.

The CRC polynomial is x8 + x5 + x4 + 1. The reset value of the SPI_CRC_DAT register is zero, and the final

value is ones-complemented before it is sent out. Note that CRC computation only includes the bits sent out on

SDO and does not include the bits of the SPI_CRC_DAT itself; thus it is okay to read SPI_CRC_DAT repeatedly.

The drdyb signal normally deasserts (active high) every 1/ODR second or when the LSB of ADC_DOUTL is read.

However, this behavior can be changed so that drdyb deassertion can occur after SPI_CRC_DAT is read, but not

later than normal DRDYB deassertion which occurs at every 1/ODR seconds. This is done by setting bit

DRDYB_AFT_CRC high.

The timing protocol for CRC can be found in Figure 60.

Figure 60. Timing Protocol for Reading SPI_CRC_DAT

If SPI_CRC_DAT read extends beyond the normal DRDYB deassertion at every 1/ODR seconds, then

CRC_RST has to be set in the SPI Data Ready Bar Control Register. This is done to avoid a CRC reset at the

DRDYB deassertion.Timing protocol for reading CRC with CRC_RST set is shown in Figure 61.

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