LMP90100MHESLASHNOPB datasheet(44/69 Pages) TI1

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ADC_DOUT

(

)

GAIN

(VINP - VINN) x

VREFP - VREFN

LMP90100

SNAS510P – JANUARY 2011 – REVISED MARCH 2013

www.ti.com

APPLICATIONS INFORMATION

QUICK START

This section shows step-by-step instructions to configure the LMP90xxx to perform a simple DC reading from

CH0.

1. Apply VA = VIO = VREFP1 = 5V, and ground VREFN1

2. Apply VINP = ¾VREF and VINN = ¼VREF for CH0. Thus, set CH0 = VIN = VINP - VINN = ½VREF

(CH0_INPUTCN register)

3. Set gain = 1 (CH0_CONFIG: GAIN_SEL = 0x0)

4. Exclude the buffer from the signal path (CH0_CONFIG: BUF_EN = 1)

5. Set the background to BgcalMode2 (BGCALCN = 0x2)

6. Select VREF1 (CH0_INPUTCN: VREF_SEL = 0)

7. To use the internal CLK, set CLK_EXT_DET = 1 and CLK_SEL = 0.

8. Follow the register read/write protocol (Figure 51) to capture ADC_DOUT from CH0.

CONNECTING THE SUPPLIES

VA and VIO

Any ADC architecture is sensitive to spikes on the analog voltage, VA, digital input/output voltage, VIO, and

ground pins. These spikes may originate from switching power supplies, digital logic, high power devices, and

other sources. To diminish these spikes, the LMP90xxx’s VA and VIO pins should be clean and well bypassed. A

0.1 µF ceramic bypass capacitor and a 1 µF tantalum capacitor should be used to bypass the LMP90xxx

supplies, with the 0.1 µF capacitor placed as close to the LMP90xxx as possible.

Since the LMP90xxx has both external VA and VIO pins, the user has two options on how to connect these pins.

The first option is to tie VA and VIO together and power them with the same power supply. This is the most cost

effective way of powering the LMP90xxx but is also the least ideal because noise from VIO can couple into VA

and negatively affect performance. The second option involves powering VA and VIO with separate power

supplies. These supply voltages can have the same amplitude or they can be different.

VREF

Operation with VREF below VA is also possible with slightly diminished performance. As VREF is reduced, the

range of acceptable analog input voltages is also reduced. Reducing the value of VREF also reduces the size of

the LSB. When the LSB size goes below the noise floor of the LMP90xxx, the noise will span an increasing

number of codes and performance will degrade. For optimal performance, VREF should be the same as VA and

sourced with a clean source that is bypassed with a ceramic capacitor value of 0.1 µF and a tantalum capacitor

of 10 µF.

LMP90xxx also allows ratiometric connection for noise immunity reasons. A ratiometric connection is when the

ADC’s VREFP and VREFN are used to excite the input device’s (i.e. a bridge sensor) voltage references. This

type of connection severely attenuates any VREF ripple seen the ADC output, and is thus strongly

recommended.

ADC_DOUT CALCULATION

The output code of the LMP90xxx can be calculated as:

Equation 1 — Output Code

(15)

ADC_DOUT is in 24

−bit two's complement binary format. The largest positive value is 0x7F_FFFF while the

largest negative value is 0x80_0000. In case of an over range the value is automatically clamped to one of these

two values.

Figure 63 shows the theoretical output code, ADC_DOUT, vs. analog input voltage, VIN, using the equation

above.

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