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LMP90100MHE/NOPB Datasheet(PDF) 36 Page - Texas Instruments |
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LMP90100MHE/NOPB Datasheet(HTML) 36 Page - Texas Instruments |
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36 / 69 page ![]() R/WB = Read/Write Data 0: Write Data 1: Read Data 7 [3:0] [N:0] R/WB SZ SZ = Size 0x0: 1 byte 0x1: 2 bytes 0x2: 3 bytes 0x3: Streaming ± 3+ bytes until CSB is de-asserted [6:5] 4 0 Lower Register Address (LRA) Data Byte (s) Instruction Byte 2 (INST2) Data Byte (s) [7:0] [7:3] [2:0] 0x0 Upper Register Address (URA) Instruction Byte 1 (INST1) Upper Address Byte (UAB) R/WB = Read/Write Address 0x10: Write Address 0x90: Read Address RA/WAB Transaction 2 ± Data Access Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA. LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Register Read/Write Protocol Figure 51 shows the protocol how to write to or read from a register. Transaction 1 sets up the upper register address (URA) where the user wants to start the register-write or register-read. Transaction 2 sets the lower register address (LRA) and includes the Data Byte(s), which contains the incoming data from the master or outgoing data from the LMP90xxx. Examples of register-reads or register-writes can be found in REGISTER READ/WRITE EXAMPLES. Figure 51. Register Read/Write Protocol Streaming When writing/reading 3+ bytes, the user must operate the device in Normal Streaming mode or Controlled Streaming mode. In the Normal Streaming mode, which is the default mode, data runs continuously starting from ADDR until CSB deasserts. This mode is especially useful when programming all the configuration registers in a single transaction. See Normal Streaming Example for an example of the Normal Streaming mode. In the Controlled Streaming mode, data runs continuously starting from ADDR until the data has run through all (STRM_RANGE + 1) registers. For example, if the starting ADDR is 0x1C, STRM_RANGE = 5, then data will be written to or read from the following ADDRs: 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21. Once the data reaches ADDR 0x21, LMP90xxx will wrap back to ADDR 0x1C and repeat this process until CSB deasserts. See Controlled Streaming Example for an example of the Controlled Streaming mode. 36 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP90100 |
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