LMP90100MHESLASHNOPB datasheet(24/69 Pages) TI1

24 / 69 page

Clock

Options

Connect a XTAL

to XIN and XOUT

Connect an external

CLK source to the

XIN/CLK pin

Is there a XTAL

connected to XIN and

XOUT?

Set CLK_EXT_DET = 1 to

E\SDVV WKH ³([WHUQDO-Clock

'HWHFWLRQ´ PRGH

Yes

Set CLK_SEL = 0 to select

the internal clock

LMP90100 will use the

internal clock

LMP90100 will

automatically detect

and use the XTAL if

CLK_EXT_DET = 0

(default)

Internal CLK

External

XTAL

External CLK Source

LMP90100 will

automatically use the

external CLK source

LMP90100

SNAS510P – JANUARY 2011 – REVISED MARCH 2013

www.ti.com

Figure 36. CLK Register Settings

The recommended value for the external CLK is discussed in the next sections.

Programmable ODRs

If using the internal CLK or external CLK of 3.5717 MHz, then the output date rates (ODR) can be selected

(using the ODR_SEL bit) as:

1. 13.42/8 = 1.6775 SPS

2. 13.42/4 = 3.355 SPS

3. 13.42/2 = 6.71SPS

4. 13.42 SPS

5. 214.65/8 = 26.83125 SPS

6. 214.65/4 = 53.6625 SPS

7. 214.65/2 = 107.325 SPS

8. 214.65 SPS (default)

If the internal CLK is not being used and the external CLK is not 3.5717 MHz, then the ODR will be different. If

this is the case, use the equation below to calculate the new ODR values.

ODR_Base1 = (CLKEXT) / (266,240)

(3)

ODR_Base2 = (CLKEXT) / (16,640)

(4)

ODR1 = (ODR_Base1) / n, where n = 1,2,4,8

(5)

ODR2 = (ODR_Base2) / n, where n = 1,2,4,8

(6)

For example, a 3.6864 MHz XTAL or external clock has the following ODR values:

ODR_Base1 = (3.6864 MHz) / (266,240) = 13.85 SPS

(7)

ODR_Base2 = (3.6864 MHz) / (16,640) = 221.54 SPS

(8)

ODR1 = (13.85 SPS) / n = 13.85, 6.92, 3.46, 1.73 SPS

(9)

ODR2 = (221.54 SPS) / n = 221.54, 110.77, 55.38, 27.69 SPS

(10)

The ODR is channel specific, which means that one channel can have one ODR, while another channel can

have the same or a different ODR.

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