LMP90100MHESLASHNOPB datasheet(37/69 Pages) TI1

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DRDYB:

SDO:

1/ODR

tDRDYB

DRDYB:

SDO:

LSB

. . .

LSB

1/ODR

LMP90100

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SNAS510P – JANUARY 2011 – REVISED MARCH 2013

If streaming reaches ADDR 0x7F, then it will wrap back to ADDR 0x00. Furthermore, reading back the Upper

To stream, write 0x3 to INST2’s SZ bits as seen in Figure 51. To select the stream type, program the

SPI_STREAMCN: STRM_TYPE bit. The STRM_RANGE can also be programmed in the same register.

CSB - Chip Select Bar

An SPI transaction begins when the master asserts (active low) CSB and ends when the master deasserts

(active high) CSB. Each transaction might be separated by a subsequent one with a CSB deassertion, but this is

optional. Once CSB is asserted, it must not pulse (deassert and assert again) during a (desired) transaction.

CSB can be grounded in systems where LMP90xxx is the only SPI slave. This frees the software from handling

the CSB. Care has to be taken to avoid any false edge on SCLK, and while operating in this mode, the streaming

transaction should not be used because exiting from this mode can only be done through a CSB deassertion.

SPI Reset

SPI Reset resets the SPI-Protocol State Machine by monitoring the SDI for at least 73 consecutive 1's at each

SCLK rising edge. After an SPI Reset, SDI is monitored for a possible Write Instruction at each SCLK rising

edge.

SPI Reset will reset the Upper Address Register (URA) to 0, but the register contents are not reset.

By default, SPI reset is disabled, but it can be enabled by writing 0x01 to SPI Reset Register (ADDR 0x02).

DRDYB - Data Ready Bar

DRDYB is a signal generated by the LMP90xxx that indicates a fresh conversion data is available in the

ADC_DOUT registers.

DRDYB is automatically asserted every (1/ODR) second and deasserts when ADC_DOUT is completely read out

(LSB of ADC_DOUTL) (Figure 52).

Figure 52. DRDYB Behavior for a Complete ADC_DOUT Reading

If ADC_DOUT is not completely read out (Figure 53) or is not read out at all, but a new ADC_DOUT is available,

then DRDYB will automatically pulse for tDRDYB second. The value for tDRDYB can be found in Timing Diagrams.

Figure 53. DRDYB Behavior for an ADC_DOUT not Read

If ADC_DOUT is being read, while the new ADC_DOUT becomes available, then the ADC_DOUT that is being

read is still valid (Figure 54). DRDYB will be deasserted at the LSB of the data being read, but a consecutive

read on the ADC_DOUT register will fetch the newly converted data available.

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LMP90100MHE/NOPB Datasheet(PDF) 37 Page - Texas Instruments

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