LMP90100MHESLASHNOPB datasheet(38/69 Pages) TI1

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LMP90100

SCLK

CSB

SDI

SDO/

DRDYB

SCLK

CSB

MOSI

MISO

INT

1/ODR

SDO

LSB

D6 = drdyb

Valid

ADC_DOUT

(ADC Data 1)

MSB

LSB

Valid

ADC_DOUT

(ADC Data 2)

MSB

ADC

Data

ADC

Data

LMP90100

SNAS510P – JANUARY 2011 – REVISED MARCH 2013

www.ti.com

Figure 54. DRDYB Behavior for an Incomplete ADC_DOUT Reading

DRDYB can also be accessed via registers using the DT_AVAIL_B bit. This bit indicates when fresh conversion

data is available in the ADC_DOUT registers. If new conversion data is available, then DT_AVAIL_B = 0;

otherwise, DT_AVAIL_B = 1.

As opposed to the drdyb signal, a complete reading for DT_AVAIL_B occurs when the MSB of ADC_DOUTH is

read out. This bit cannot be reset even if REG_AND_CNV_RST = 0xC3.

DrdybCase1: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x00

Figure 55. DrdybCase1 Connection Diagram

As shown in Figure 55, the drdyb signal and SDO can be multiplexed on the same pin as their functions are

mostly complementary. In fact, this is the default mode for the SDO/DRDYB pin.

Figure 56 shows a timing protocol for DrdybCase1. In this case, start by asserting CSB first to monitor a drdyb

assertion. When the drdyb signal asserts, begin writing the Instruction Bytes (INST1, UAB, INST2) to read from

or write to registers. Note that INST1 and UAB are omitted from the figure below because this transaction is only

required if a new UAB needs to be implemented.

While the CSB is asserted, DRDYB is driving the SDO/DRDYB pin unless the device is reading data, in which

case, SDO will be driving the pin. If CSB is deasserted, then the SDO/DRDYB pin is High-Z.

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LMP90100MHE/NOPB Datasheet(PDF) 38 Page - Texas Instruments

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