LMP90100MHESLASHNOPB datasheet(61/69 Pages) TI1

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LMP90100

www.ti.com

SNAS510P – JANUARY 2011 – REVISED MARCH 2013

Table 31. DATA_ONLY_2: Data Only Read Control 2 (Address 0x0A)

Bit

Bit Symbol

Bit Description

[7:3]

Reserved

[2:0]

Number of bytes to be read out in Data Only mode. A value of 0x0 means read one byte and 0x7

means read 8 bytes.

DATA_ONLY_SZ

Default: 0x2

Table 32. SPI_DRDYBCN: SPI Data Ready Bar Control (Address 0x11)

Bit

Bit Symbol

Bit Description

Enable DRDYB on D6

SPI_DRDYB_D6

0 (default): D6 is a GPIO

1: D6 = drdyb signal

Reserved

CRC Reset

CRC_RST

0 (default): Enable CRC reset on DRDYB deassertion

1: Disbale CRC reset on DRDYB deassertion

Reserved

Gain background calibration

0 (default): Correct FGA gain error. This is useful only if the device is operating in BgcalMode2

FGA_BGCAL

and ScanMode2 or ScanMode3.

1: Correct FGA gain error using the last known coefficients.

[2:0]

Reserved

Default - 0x3 (do not change this value)

Table 33. SPI_CRC_CN: CRC Control (Address 0x13)

Bit

Bit Symbol

Bit Description

[7:5]

Reserved

Enable CRC

EN_CRC

0 (default): Disable CRC

1: Enable CRC

Reserved

Default - 0x0 (do not change this value)

DRDYB After CRC

DRDYB_AFT_CRC

0 (default): DRDYB is deasserted (active high) after ADC_DOUTL is read.

1: DRDYB is deasserted after SPI_CRC_DAT (which follows ADC_DOUTL), is read.

[1:0]

Reserved

Table 34. SPI_CRC_DAT: CRC Data (Address 0x1D)

Bit

Bit Symbol

Bit Description

CRC Data

When written, this register reset CRC:

[7:0]

CRC_DAT

Any Value: Reset CRC

When read, this register indicates the CRC data.

GPIO REGISTERS

Table 35. GPIO_DIRCN: GPIO Direction (Address 0x0E)

Bit

Bit Symbol

Bit Description

Reserved

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