LMP90100MHESLASHNOPB datasheet(45/69 Pages) TI1

45 / 69 page

R/WB = Read/Write Data

0: Write Data

1: Read Data

[3:0]

[23:0]

0x2

SZ = Size

0x0: 1 byte

0x1: 2 bytes

0x2: 3 bytes

0x3: Streaming ± 3+ bytes until CSB is de-asserted

[6:5]

0xF

The 1

Data Byte will be written to ADDR 0x1F, the 2

Data Byte will

be written to ADDR 0x20, and the 3

Data Byte will be written to ADR

0x21. After this process, deassert CSB.

Instruction Byte 2 (INST2)

Data Bytes

[7:0]

[7:3]

[2:0]

0x0

0x1

Instruction Byte 1 (INST1)

Upper Address Byte (UAB)

R/WB = Read/Write Address

0x10: Write Address

0x90: Read Address

0x10

Transaction 2 ± Data Access

Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.

-8,388,608d

ADC_DOUT

- 16, 777, 215d

VIN

8,388,607d

(VREF - 1LSB)

(-VREF +1LSB)

LMP90100

www.ti.com

SNAS510P – JANUARY 2011 – REVISED MARCH 2013

Figure 63. ADC_DOUT vs. VIN of a 24-Bit Resolution (VREF = 5.5V, Gain = 1).

Writing to Register Examples

Using the register read/write protocol shown in Figure 51, the following example shows how to write three data

bytes starting at register address (ADDR) 0x1F. After the last byte has been written to ADDR 0x21, deassert

CSB to end the register-write.

Figure 64. Register-Write Example 1

The next example shows how to write one data byte to ADDR 0x12. Since the URA for this example is the same

as the last example, transaction 1 can be omitted.

Submit Documentation Feedback

Product Folder Links: LMP90100

LMP90100MHE/NOPB Datasheet(PDF) 45 Page - Texas Instruments

LMP90100MHE/NOPB Datasheet(HTML) 45 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Datasheet Download

Link URL