LMP90100MHESLASHNOPB datasheet(40/69 Pages) TI1

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CSB

SCLK

INST2

SDI

MSB

LSB

Drdyb = D6

SDO

Data Byte (s)

High-Z

MSB

LSB

LMP90100

SCLK

CSB

SDI

SDO

D6 = DRDYB

SCLK

CSB

MOSI

MISO

Interrupt

LMP90100

SNAS510P – JANUARY 2011 – REVISED MARCH 2013

www.ti.com

DrdybCase3: Routing DRDYB to D6

Figure 58. DrdybCase3 Connection Diagram

The drdyb signal can be routed to pin D6 by setting SPI_DRDYB_D6 high and SDO_DRDYB_DRIVER to 0x4.

This is the behavior for DrdybCase3 as shown in Figure 58.

The timing protocol for this case can be seen in Figure 59. Since DRDYB is separated from SDO, it can be

monitored using the interrupt or polling method. If polled, the drdyb signal needs to be polled faster than tDRDYB to

detect a drdyb assertion. When drdyb asserts, assert CSB to start the SPI transaction and begin writing the

Instruction Bytes (INST1, UAB, INST2) to read from or write to registers.

Figure 59. Timing Protocol for DrdybCase3

Data Only Read Transaction

In a data only read transaction, one can directly access the data byte(s) as soon as the CSB is asserted without

having to send any instruction byte. This is useful as it brings down the latency as well as the overhead

associated with the instruction byte (as well as the Upper Address Byte, if any).

In order to use the data only transaction, the device must be placed in the data first mode. The following table

lists transaction formats for placing the device in and out of the data first mode and reading the mode status.

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