LMP90100MHESLASHNOPB datasheet(47/69 Pages) TI1

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[3:0]

[47:0]

0x3

[6:5]

0x8

The 1

Data Byte will be written to ADDR 0x28, the 2

Data Byte will be

written to ADDR 0x29, etc. The last and 6

Data Byte will be written to

ADDR 0x2D. After this process, deassert CSB.

Instruction Byte 2 (INST2)

Data Bytes

[7:0]

[7:3]

[2:0]

0x0

0x2

Instruction Byte 1 (INST1)

Upper Address Byte (UAB)

0x10

Transaction 2 ± Data Access

Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.

R/WB = Read/Write Address

0x10: Write Address

0x90: Read Address

R/WB = Read/Write Data

0: Write Data

1: Read Data

SZ = Size

0x0: 1 byte

0x1: 2 bytes

0x2: 3 bytes

0x3: Streaming ± 3+ bytes until CSB is de-asserted

LMP90100

www.ti.com

SNAS510P – JANUARY 2011 – REVISED MARCH 2013

STREAMING EXAMPLES

Normal Streaming Example

This example shows how to write six data bytes starting at ADDR 0x28 using the Normal Streaming mode.

Because the default STRM_TYPE is the Normal Streaming mode, setting up the SPI_STREAMCN register can

be omitted.

Figure 67. Normal Streaming Example

Controlled Streaming Example

This example shows how to read the 24-bit conversion data (ADC_DOUT) four times using the Controlled

Streaming mode. The ADC_DOUT registers consist of ADC_DOUTH at ADDR 0x1A, ADC_DOUTM at ADDR

0x1B, and ADC_DOUTL at ADDR 0x1C.

The first step (Figure 68) sets up the SPI_STREAMCN register. This step enters the Controlled Streaming mode

by setting STRM_TYPE high in ADDR 0x03. Since three registers (ADDR 0x1A - 0x1C) need to be read, the

STRM_RANGE is 2.

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