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LMP90100MHE/NOPB Datasheet(PDF) 46 Page - Texas Instruments |
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LMP90100MHE/NOPB Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 69 page ![]() 7 [3:0] [15:0] 1 0x1 [6:5] 4 0 0x4 2 Data Bytes will be read from ADDR 0x24 and ADDR 0x25. After this process, deassert CSB . Instruction Byte 2 (INST2) Data Bytes [7:0] [7:3] [2:0] 0x0 0x2 Instruction Byte 1 (INST1) Upper Address Byte (UAB) 0x10 Transaction 2 ± Data Access Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA. R/WB = Read/Write Address 0x10: Write Address 0x90: Read Address R/WB = Read/Write Data 0: Write Data 1: Read Data SZ = Size 0x0: 1 byte 0x1: 2 bytes 0x2: 3 bytes 0x3: Streaming ± 3+ bytes until CSB is de-asserted R/WB = Read/Write Data 0: Write Data 1: Read Data 7 [3:0] [7:0] 0 0x00 SZ = Size 0x0: 1 byte 0x1: 2 bytes 0x2: 3 bytes 0x3: Streaming ± 3+ bytes until CSB is de-asserted [6:5] 4 0 0x2 One Data Byte will be written to ADDR 0x12. After this process, deassert CSB. Instruction Byte 2 (INST2) Data Byte (s) Transaction 2 ± Data Access LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Figure 65. Register-Write Example 2 Reading from Register Example The following example shows how to read two bytes. The first byte will be read from starting ADDR 0x24, and the second byte will be read from ADDR 0x25. Figure 66. Register-Read Example 46 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP90100 |
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