M16CSLASH62P datasheet(35/349 Pages) MITSUBISHI

35 / 349 page

Bus

Mitsubishi microcomputers

M16C / 62P Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev.1.0

Specifications in this manual are tentative and subject to change.

Function

Bit symbol

Bit name

Chip select control register

Symbol

Address

After reset

CSR

000816

000000012

CS1

CS0

CS3

CS2

CS0 output enable bit

CS1 output enable bit

CS2 output enable bit

CS3 output enable bit

CS1W

CS0W

CS3W

CS2W

CS0 wait bit

CS1 wait bit

CS2 wait bit

CS3 wait bit

0 : Chip select output disabled

(functions as I/O port)

1 : Chip select output enabled

0 : With wait state

1 : Without wait state

(Note 1, Note 2, Note 3)

Note 1: Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplex bus is used, set

the CSiW bit to “0” (Wait state).

Note 2: If the PM17 bit in the PM1 register is set to “1” (with wait state), the external area indicated by CS0 to

CS3 is always accessed with one wait state even when the CSiW bit is “1” (without wait state).

Note 3: When the CSiW bit = “0” (with wait state), the number of wait states (interms of clock cycles) can be

selected using the CSEi1W to CSEi0W bits in the CSE register.

Figure 1.7.1. CSR Register

Bus Control

The following describes the signals needed for accessing external devices and the functionality of software

wait.

(1) Address Bus

The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or

20 bits by using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 1.7.1

shows the PM06 and PM11 bit set values and address bus widths.

When processor mode is changed from single-chip mode to memory extension mode, the address

bus is indeterminate until any external area is accessed.

(2) Data Bus

When input on the BYTE pin is high, 8 lines D0 to D7 comprise the data bus; when input on the BYTE

pin is low, 16 lines D0 to D15 comprise the data bus.

Do not change the input level on the BYTE pin while in operation.

(3) Chip Select Signal

______

The chip select (hereafter referred to as the CSi) signals are output from the CSi (i = 0 to 3) pins.

_____

These pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.

Figure 1.7.1 shows the CSR register.

______

During 1 Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output

______

from the CSi pin. During 4 Mbyte mode, CSi signal or bank number is output from the CSi pin. Refer to

______

“Memory space expansion function”. Figure 1.7.2 shows the example of address bus and CSi signal

output in 1 Mbyte mode.

Set value(Note)

Pin function

PM11=1

P34 to P37

Address bus wide

12 bits

PM06=1

P40 to P43

PM11=0

A12 to A15

16 bits

PM06=1

P40 to P43

PM11=0

A12 to A15

20 bits

PM06=0

A16 to A19

Note 1: No values other than those shown above can be set.

Table 1.7.1. PM06 and PM11 Bits Set Value and Address Bus Width

M16C/62P Datasheet(PDF) 35 Page - Mitsubishi Electric Semiconductor

M16C/62P Datasheet(HTML) 35 Page - Mitsubishi Electric Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL