| Electronic Components Datasheet Search |
|
M16C/62P Datasheet(PDF) 97 Page - Mitsubishi Electric Semiconductor |
|
|
|||||||||||||||||||||||||||||
M16C/62P Datasheet(HTML) 97 Page - Mitsubishi Electric Semiconductor |
|
97 / 349 page ![]() Watchdog Timer 96 Mitsubishi microcomputers M16C / 62P Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Under development Preliminary Specifications Rev.1.0 Specifications in this manual are tentative and subject to change. Watchdog timer start register (Note) Symbol Address After reset WDTS 000E16 Indeterminate WO b7 b0 Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of whatever value is written. RW Note : Write to the WDTS register after the watchdog timer interrupt occurs. Figure 1.12.2. WDC Register and WDTS Register CPU clock Write to WDTS register RESET PM12 = 0 Watchdog timer Set to “7FFF16” 1/128 1/16 CM07 = 0 WDC7 = 1 CM07 = 0 WDC7 = 0 CM07 = 1 HOLD 1/2 Prescaler PM12 = 1 Watchdog timer interrupt request Reset PM22 = 0 PM22 = 1 Ring oscillator clock Figure 1.12.1. Watchdog Timer Block Diagram Watchdog timer control register Symbol Address After reset WDC 000F16 00XXXXXX2(Note2) Function Bit symbol RW b7 b6 b5 b4 b3 b2 b1 b0 High-order bit of watchdog timer WDC7 Bit name Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Reserved bit Must set to “0” 0 RO RW RW RW Cold start / warm start discrimination flag (Note 1) 0 : Cold start 1 : Warm start WDC5 Note 1: The WDC5 bit is always “1” (warm start) no matter how it is set by writing a “0” or “1”. Note 2: The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set to “0” when the input voltage at the VCC1 pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to “1” (RAM retention limit detection circuit enable). (b4-b0) (b6) Setting the PM22 bit to “1” results in the following conditions • The ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source. • The CM10 bit of CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode entered.) • The watchdog timer does not stop when in wait mode or hold state. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |