M16CSLASH62P datasheet(70/349 Pages) MITSUBISHI

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Clock Generation Circuit

Mitsubishi microcomputers

M16C / 62P Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev.1.0

Specifications in this manual are tentative and subject to change.

Figure 1.9.11. State Transition in Normal Mode

CM04=0

CPU clock: f(PLL)

CM07=0

CM06=0

CM17=0

CM16=0

PLL operation mode

CM07=0

CM06=0

CM17=0

CM16=0

CM07=0

CM17=0

CM06=0

CM16=0

CM07=0

CM17=0

CM06=0

CM16=1

CM07=0

CM17=1

CM06=0

CM16=0

CM07=0

CM06=1

CM07=0

CM17=1

CM06=0

CM16=1

High-speed mode

CM07=0

CM17=0

CM06=0

CM16=0

CM07=0

CM17=0

CM06=0

CM16=1

CM07=0

CM17=1

CM06=0

CM16=0

CM07=0

CM06=1

CM07=0

CM17=1

CM06=0

CM16=1

CM07=0

Low-speed mode

CM07=0

Low power dissipation mode

CM06=1

CM15=1

Ring oscillator mode

CPU clock

Ring oscillator

mode

CPU clock

Ring oscillator

low power

dissipation mode

CPU clock

CM07=0

Low-speed mode

CM07=0

Low power

dissipation mode

CM06=1

CM15=1

PLC07=1

CM11=1

(Note 6)

PLC07=0

CM11=0

(Note 7)

CM04=0

PLC07=1

CM11=1

PLC07=0

CM11=0

CM04=0

CM04=1

CM04=0

CM04=1

CM07=0

(Note 2, Note 4)

CM07=1

(Note 3)

CM05=1

(Note 1)

CM05=0

CM05=1

(Note 1)

CM21=0

(Note 8)

CM21=1

CM21=0

(Note 8)

CM21=1

CM21=0

CM21=1

CM21=0

CM21=1

Main clock oscillation

Ring oscillator clock

oscillation

Sub clock oscillation

f(Ring)

f(Ring)/2

f(Ring)/4

f(Ring)/8

f(Ring)/16

f(Ring)

f(Ring)/2

f(Ring)/4

f(Ring)/8

f(Ring)/16

f(Ring)

f(Ring)/2

f(Ring)/4

f(Ring)/8

f(Ring)/16

f(Ring)

f(Ring)/2

f(Ring)/4

f(Ring)/8

f(Ring)/16

PLL operation

mode

CPU clock: f(PLL)

CPU clock: f(XIN)

High-speed mode

Middle-speed mode

(divide by 2)

CPU clock: f(XIN)/2

CPU clock: f(XIN)/4

CPU clock: f(XIN)/8

CPU clock: f(XIN)/16

CPU clock: f(XCIN)

CM05=0

CM05=1

(Note 1)

CM05=1

(Note 1)

CM05=0

(Note 6)

(Note 7)

Middle-speed mode

(divide by 4)

Middle-speed mode

(divide by 8)

Middle-speed mode

(divide by 16)

Middle-speed mode

(divide by 2)

Middle-speed mode

(divide by 4)

Middle-speed mode

(divide by 8)

Middle-speed mode

(divide by 16)

CPU clock: f(XIN)

CPU clock: f(XIN)/2

CPU clock: f(XIN)/4

CPU clock: f(XIN)/8

CPU clock: f(XIN)/16

Ring oscillator low power

dissipation mode

Notes:

1: Avoid making a transition when the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled).

Set the CM20 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.

2: Switch clock after oscillation of main clock is sufficiently stable.

3: Switch clock after oscillation of sub-clock is sufficiently stable.

4: Change CM17 and CM16 before changing CM06.

5: Transit in accordance with arrow.

6: PLL operation mode can only be entered from high speed mode. Also, wait until the PLL clock is sufficiently stable before changing operation modes.

To select a 16 MHz or higher PLL clock, set the PM20 bit to “0” (SFR accessed with two wait states) before setting PLC07 to “1” (PLL operation).

7: PLL operation mode can only be changed to high speed mode. If the PM20 bit = 0 (SFR accessed with two wait states), set PLC07 to “0” (PLL turned off)

before setting the PM20 bit to “1” (SFR accessed with one wait state).

8: Set the CM06 bit to “1” (division by 8 mode) before changing back the operation mode from ring oscillator mode to high- or middle-speed mode.

M16C/62P Datasheet(PDF) 70 Page - Mitsubishi Electric Semiconductor

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