M16CSLASH62P datasheet(94/349 Pages) MITSUBISHI

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Interrupts

Mitsubishi microcomputers

M16C / 62P Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev.1.0

Specifications in this manual are tentative and subject to change.

Precautions for Interrupts

(1) Reading Address 0000016

• Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the

CPU reads interrupt information (interrupt number and interrupt request priority level) from the address

0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.

If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority

among the enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or

an unexpected interrupt is generated.

(2) SP Setting

• Set any value in the SP before accepting an interrupt. The SP is cleared to ‘000016’ after reset. There-

fore, if an interrupt is accepted before setting any value in the SP, the program may go out of control.

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Especially when using NMI interrupt, set a value in the SP at the beginning of the program. For the first

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and only the first instruction after reset, all interrupts including NMI interrupt are disabled.

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(3) NMI Interrupt

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• The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC via a

resistor (pull-up).

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• The input level of the NMI pin can be read by accessing the P8 register’s P8_5 bit. Note that the P8_5 bit

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can only be read when determining the pin level after an NMI interrupt is generated.

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• Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on the

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NMI pin is low the CM1 register’s CM10 bit is fixed to “0”.

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• Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin

goes low, the CPU stops but CPU clock remains active; therefore, the current consumption in the chip

does not drop. In this case, normal condition is restored by an interrupt generated thereafter.

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• The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles +

300 ns or more.

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(4) INT Interrupt

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• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to the INT0

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through INT5 pins regardless of the CPU clock.

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• When the polarity of the INT0 to INT5 pins is changed, the IR bit is sometimes set to “1” (=interrupt

requested). After changing the polarity, set the IR bit to “0” (=interrupt not requested). Figure 1.11.13

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shows the procedure for changing the INT interrupt generate factor.

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Figure 1.11.14. Switching Procedure for INT Interrupt Request

Set the ILVL2 to ILVL0 bits to '0002' (= level 0)

(Disable INT interrupt)

Set the POL bit

Set the ILVL2 to ILVL0 bits to

'0012' (=level 1) to '1112' (=level 7)

(Enable the accepting of INT interrupt request)

Set the I flag to “0” (=disable interrupt)

Set the I flag to “1” (= enable interrupt)

Note: Execute the setting above individually. Do not execute two or

more settings at once (by one instruction).

Set the IR bit to “0” (=interrupt not requested)

M16C/62P Datasheet(PDF) 94 Page - Mitsubishi Electric Semiconductor

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