M16CSLASH62P datasheet(48/349 Pages) MITSUBISHI

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Mitsubishi microcomputers

M16C / 62P Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Memory Space Expansion Function

Under

development

Preliminary Specifications Rev.1.0

Specifications in this manual are tentative and subject to change.

Figure 1.8.6 shows the external memory connect example in 4 Mbyte mode.

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In this example, the CS pin of 4-Mbyte ROM is connected to the CS0 pin of microcomputer. The address

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input AD21, AD20 and AD19 pins are connected to the CS3, CS2 and CS1 pins of microcomputer,

respectively. The address input AD18 pin is connected to the A19 pin of microcomputer. Figures 1.8.7 to

1.8.9 show the relationship of addresses between the 4-Mbyte ROM and the microcomputer for the case

of a connection example in Figure 1.8.6.

In microprocessor mode, or in memory expansion mode where the PM13 bit is “0”, banks are located

every 512 Kbytes. Setting the OFS bit to “1” allows the accessed address to be offset by 4000016, so that

even the data overlapping a bank boundary can be accessed in succession.

In memory expansion mode where the PM13 bit is “1”, each 512-Kbyte bank can be accessed in 256

Kbyte units by switching them over with the OFS bit.

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Because the SRAM can be accessed on condition that the chip select signals S2 = “H” and S1 =“L”, CS0

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and CS2 can be connected to S2 and S1, respectively. If the SRAM does not have the input pins to accept

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“H” active and “L” active chip select signals, CS0 and CS2 should be decoded external to the chip.

D0 to D7

A0 to A16

A17

CS1

CS2

CS3

CS0

A19

DQ0 to DQ7

AD0 to AD16

AD17

AD18

AD19

DQ0 to DQ7

AD0 to AD16

AD20

AD21

Note: If only one chip select pin (S1 or S2) is present,

decoding by use of an external circuit is required.

(Note)

Figure 1.8.6. External Memory Connect Example in 4M Byte Mode

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