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M16C/62P Datasheet(PDF) 78 Page - Mitsubishi Electric Semiconductor |
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M16C/62P Datasheet(HTML) 78 Page - Mitsubishi Electric Semiconductor |
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78 / 349 page ![]() Interrupts 77 Mitsubishi microcomputers M16C / 62P Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Under development Preliminary Specifications Rev.1.0 Specifications in this manual are tentative and subject to change. Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. (1) Special Interrupts Special interrupts are non-maskable interrupts. _______ • NMI Interrupt _______ _______ An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details _______ about the NMI interrupt, refer to the section "NMI interrupt". ________ • DBC Interrupt Do not normally use this interrupt because it is provided exclusively for use by development support tools. • Watchdog Timer Interrupt Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer. For details about the watchdog timer, refer to the section "watchdog timer". • Oscillation Stop and Re-oscillation Detection Interrupt Generated by the oscillation stop and re-oscillation detection function. For details about the oscilla- tion stop detection function, refer to the section "clock generating circuit". • Power Supply Down Detection Interrupt Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to the section "voltage detection circuit". • Single-step Interrupt Do not normally use this interrupt because it is provided exclusively for use by development support tools. • Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMAD0 to RMAD3 register that corresponds to one of the AIER register’s AIER0 or AIER1 bit or the AIER2 register’s AIER20 or AIER21 bit which is "1" (address match interrupt en- abled). For details about the address match interrupt, refer to the section "address match interrupt". (2) Peripheral Function Interrupts Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal functions. The interrupt sources for peripheral function interrupts are listed in Table 1.11.2. For details about the peripheral functions, refer to the description of each peripheral function in this manual. |
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