M16CSLASH62P datasheet(87/349 Pages) MITSUBISHI

87 / 349 page

Mitsubishi microcomputers

M16C / 62P Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupts

Under

development

Preliminary Specifications Rev.1.0

Specifications in this manual are tentative and subject to change.

Figure 1.11.7. Operation of Saving Register

(2) SP contains odd number

[SP]

(Odd)

[SP] – 1 (Even)

[SP] – 2(Odd)

[SP] – 3 (Even)

[SP] – 4(Odd)

[SP] – 5 (Even)

Address

Sequence in which order

registers are saved

(2)

(1)

Finished saving registers

in four operations.

(3)

(4)

(1) SP contains even number

[SP]

(Even)

[SP] – 1(Odd)

[SP] – 2 (Even)

[SP] – 3(Odd)

[SP] – 4 (Even)

[SP] – 5 (Odd)

Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.

After registers are saved, the SP content is [SP] minus 4.

Address

PCM

Stack

FLGL

PCL

Sequence in which order

registers are saved

(2) Saved simultaneously,

all 16 bits

(1) Saved simultaneously,

all 16 bits

Finished saving registers

in two operations.

PCM

Stack

FLGL

PCL

Saved, 8 bits at a time

FLGH

PCH

FLGH

PCH

The operation of saving registers carried out in the interrupt sequence is dependent on whether the

SP(Note), at the time of acceptance of an interrupt request, is even or odd. If the stack pointer (Note) is

even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits

at a time. Figure 1.11.7 shows the operation of the saving registers.

Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated

by the U flag. Otherwise, it is the ISP.

M16C/62P Datasheet(PDF) 87 Page - Mitsubishi Electric Semiconductor

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