M16CSLASH62P datasheet(85/349 Pages) MITSUBISHI

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Mitsubishi microcomputers

M16C / 62P Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupts

Under

development

Preliminary Specifications Rev.1.0

Specifications in this manual are tentative and subject to change.

Interrupt sources

Level that is set to IPL

_______

Watchdog timer, NMI

_________

Software, address match, DBC, single-step

Not changed

Variation of IPL when Interrupt Request is Accepted

When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set

in the IPL.

When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed

in Table 1.11.5 is set in the IPL. Shown in Table 1.11.5 are the IPL values of software and special

interrupts when they are accepted.

Table 1.11.5. IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted

Instruction

Interrupt sequence

Instruction in

interrupt routine

Time

Interrupt response time

(a)

(b)

Interrupt request acknowledged

Interrupt request generated

(a) A time from when an interrupt request is generated till when the instruction then

executing is completed. The length of this time varies with the instruction being

executed. The DIVX instruction requires the longest time, which is equal to 30 cycles

(without wait state, the divisor being a register).

(b) A time during which the interrupt sequence is executed. For details, see the table

below. Note, however, that the values in this table must be increased 2 cycles for the

DBC interrupt and 1 cycle for the address match and single-step interrupts.

Interrupt vector address

Even

Odd

SP value

Even

Odd

Even

Odd

16-Bit bus, without wait

18 cycles

19 cycles

20 cycles

8-Bit bus, without wait

20 cycles

Figure 1.11.5. Interrupt response time

Interrupt Response Time

Figure 1.11.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time

denotes a time from when an interrupt request is generated till when the first instruction in the interrupt

routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when

the instruction then executing is completed ((a) in Figure 1.11.5) and a time during which the interrupt

sequence is executed ((b) in Figure 1.11.5).

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