M16CSLASH62P datasheet(71/349 Pages) MITSUBISHI

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Mitsubishi microcomputers

M16C / 62P Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock Generation Circuit

Under

development

Preliminary Specifications Rev.1.0

Specifications in this manual are tentative and subject to change.

Table 1.9.7. Allowed Transition and Setting

High-speed mode,

middle-speed mode

Ring oscillator mode

Stop mode

Wait mode

Ring oscillator

low power dissipation

mode

PLL operation mode2

Low power dissipation

mode2

Low-speed mode2

State after transition

See Table A

(8)

(18)5

(3)

(4)

(5)

(7)

(5)

(7)

(6)

division

Divided

by 2

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

(15)

(16)

(17)

(18)

Setting

Operation

CM04 = 0

Sub clock turned off

CM04 = 1

Sub clock oscillating

CM06 = 0,

CPU clock no division mode

CM17 = 0 , CM16 = 0

CM06 = 0,

CPU clock division by 2 mode

CM17 = 0 , CM16 = 1

CM06 = 0,

CPU clock division by 4 mode

CM17 = 1 , CM16 = 0

CM06 = 1

CPU clock division by 8 mode

CM06 = 0,

CPU clock division by 16 mode

CM17 = 1 , CM16 = 1

CM07 = 0

Main clock, PLL clock,

or ring oscillator clock selected

CM07 = 1

Sub clock selected

CM05 = 0

Main clock oscillating

CM05 = 1

Main clock turned off

PLC07 = 0,

CM11 = 0

Main clock selected

PLC07 = 1,

CM11 = 1

PLL clock selected

CM21 = 0

Main clock or PLL clock selected

CM21 = 1

Ring oscillator clock selected

CM10 = 1

Transition to stop mode

wait

Transition to wait mode

Hardware interrupt

Exit stop mode or wait mode

(9)7

(10)

(11)1, 6

(12)3

(14)4

(13)3

(15)

(10)

(18)

(16)1

(17)

(16)1

(17)

(16)1

(17)

(16)1

(17)

(16)1

(17)

(3)

(4)

(5)

(7)

(6)

(1)

(2)

Sub clock oscillating

Sub clock turned off

(18)5

(18)

Table 1. State Transition with Main Clock Division Ration in High- or Middle-speed Mode,

Ring Oscillator Mode, and Ring Oscillator Low Power Dissipation Mode

Table B. Setting and Operation

Notes:

1. Avoid making a transition when the CM21 bit is set to “1” (oscillation stop, re-oscillation detection function enabled).

Set the CM21 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.

2. Ring oscillator clock oscillates and stops in low-speed mode and low power dissipation mode. In these mode,

the ring oscillator can be used as peripheral function clock.

Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as peripheral function

clock.

3. PLL operation mode can only be entered from and changed to high-speed mode.

4. Set the CM06 bit to “1” (division by 8 mode) before transiting from ring oscillator mode to high- or middle-speed mode.

5. When exiting stop mode, the CM06 bit is set to “1” (division by 8 mode).

6. If the CM05 bit is set to “1” (main clock stop), then the CM06 bit is set to “1” (division by 8 mode).

7. A transition can be made only when sub clock is oscillating.

--: Cannot transit

(11)1

--: Cannot transit

High-speed mode,

middle-speed mode

Ring oscillator

mode

Stop mode

Wait mode

Ring oscillator

low power

dissipation mode

PLL operation

mode1

Low power

dissipation mode1

Low-speed mode1

See Table A

Divided

by 4

Divided

by 8

Divided

by 16

division

Divided

by 2

Divided

by 4

Divided

by 8

Divided

by 16

No division

Divided by 4

Divided by 8

Divided by 16

Divided by 2

No division

Divided by 4

Divided by 8

Divided by 16

Divided by 2

M16C/62P Datasheet(PDF) 71 Page - Mitsubishi Electric Semiconductor

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