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XC2230L Datasheet(PDF) 101 Page - Infineon Technologies AG |
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XC2230L Datasheet(HTML) 101 Page - Infineon Technologies AG |
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101 / 112 page ![]() XC2230L, XC2234L XC2000 Family / Econo Line Electrical Parameters Data Sheet 97 V1.3, 2015-02 4.7.6 Debug Interface Timing The debugger can communicate with the XC223[04]L via 1-pin SPD interface, via the 2- pin DAP interface or via the standard JTAG interface. Debug via DAP The following parameters are applicable for communication through the DAP debug interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Table 36 is valid under the following conditions: C L= 20 pF; voltage_range= upper Table 36 DAP Interface Timing for Upper Voltage Range Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. DAP0 clock period t 11 SR 100 1) 1) The debug interface cannot operate faster than the overall system, therefore t 11 ≥ tSYS. −− ns DAP0 high time t 12 SR 8 −− ns DAP0 low time t 13 SR 8 −− ns DAP0 clock rise time t 14 SR −− 4ns DAP0 clock fall time t 15 SR −− 4ns DAP1 setup to DAP0 rising edge t 16 SR 6 −− ns pad_type= stan dard DAP1 hold after DAP0 rising edge t 17 SR 6 −− ns pad_type= stan dard DAP1 valid per DAP0 clock period 2) 2) The Host has to find a suitable sampling point by analyzing the sync telegram response. t 19 CC 92 95 − ns pad_type= stan dard |
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