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XC2230L Datasheet(PDF) 105 Page - Infineon Technologies AG |
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XC2230L Datasheet(HTML) 105 Page - Infineon Technologies AG |
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105 / 112 page ![]() XC2230L, XC2234L XC2000 Family / Econo Line Electrical Parameters Data Sheet 101 V1.3, 2015-02 Table 39 is valid under the following conditions: C L= 20 pF; voltage_range= lower Table 39 JTAG Interface Timing for Lower Voltage Range Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. TCK clock period t 1 SR 100 1) 1) The debug interface cannot operate faster than the overall system, therefore t 1 ≥ tSYS. −− ns TCK high time t 2 SR 16 −− ns TCK low time t 3 SR 16 −− ns TCK clock rise time t 4 SR −− 8ns TCK clock fall time t 5 SR −− 8ns TDI/TMS setup to TCK rising edge t 6 SR 6 −− ns TDI/TMS hold after TCK rising edge t 7 SR 6 −− ns TDO valid from TCK falling edge (propagation delay) 2) 2) The falling edge on TCK is used to generate the TDO timing. t 8 CC − 39 43 ns TDO high impedance to valid output from TCK falling edge 3)2) 3) The setup time for TDO is given implicitly by the TCK cycle time. t 9 CC − 39 43 ns TDO valid output to high impedance from TCK falling edge 2) t 10 CC − 39 43 ns TDO hold after TCK falling edge 2) t 18 CC 5 −− ns |
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