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XC2230L Datasheet(PDF) 104 Page - Infineon Technologies AG |
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XC2230L Datasheet(HTML) 104 Page - Infineon Technologies AG |
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104 / 112 page ![]() XC2230L, XC2234L XC2000 Family / Econo Line Electrical Parameters Data Sheet 100 V1.3, 2015-02 Debug via JTAG The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Table 38 is valid under the following conditions: C L= 20 pF; voltage_range= upper Table 38 JTAG Interface Timing for Upper Voltage Range Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. TCK clock period t 1 SR 100 1) 1) The debug interface cannot operate faster than the overall system, therefore t 1 ≥ tSYS. −− ns 2) 2) Under typical conditions, the JTAG interface can operate at transfer rates up to 10 MHz. TCK high time t 2 SR 16 −− ns TCK low time t 3 SR 16 −− ns TCK clock rise time t 4 SR −− 8ns TCK clock fall time t 5 SR −− 8ns TDI/TMS setup to TCK rising edge t 6 SR 6 −− ns TDI/TMS hold after TCK rising edge t 7 SR 6 −− ns TDO valid from TCK falling edge (propagation delay) 3) 3) The falling edge on TCK is used to generate the TDO timing. t 8 CC − 29 32 ns TDO high impedance to valid output from TCK falling edge 4)3) 4) The setup time for TDO is given implicitly by the TCK cycle time. t 9 CC − 29 32 ns TDO valid output to high impedance from TCK falling edge 3) t 10 CC − 29 32 ns TDO hold after TCK falling edge 3) t 18 CC 5 −− ns |
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